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asynchronous to synchronous design
Reference the question posted on Nov21, and the reply received from ahedin the answer is as follows - I am using the 8 times system clock to write into the dual port RAM and not the data which comes with the clock. If the same clock were used then since the two clocks are not phase-locked... -
asynchronous to synchronous design
I am trying to design an asynchronous to synchronous design within a FPGA (Field programmable gate array) but have been unsuccessful so far. The exact problem is as follows : There is a pseudo-random data stream coming at approximately 8 Mbps with respect to a 8MHz clock. The data can vary...
