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fayevalentine, I tried this piece of code with Altera tools, but it gives me an empty result. Maybe Xilinx is working different then? All I wanted, was to test something because I noticed that integer J has no range, and is allowed to count to infinity, well actually 2147483647. This brings...

Hello Oppenheimer, I examined your last code. The variable value is not clocked, clk is in the sensitivity list of the process but you forgot to include the rising_edge(clk) statement. The same goes for the data outputs. Also signal bcd is not driving anything and can be skipped. Good luck...

Hello Oppenheimer, I think the following piece of code is causing the trouble. Data<= zero after 500 ms; You can't use a delay this way in RTL. The compiler doesn't understand this. You have to define your delay in another way. You can use this in Testbenches to test your design by raising...

Hello Clementval, X's means usually unknown value's. Are you sure you have a proper reset during simulation? Good luck

Hello Nealmurray, I think the problem is in the following line. IF (CLK'event AND CLK='1' and Q < 9300) THEN I dont think you can have the Q condition check within a clk event. Better is to sepperate them. IF (CLK'event AND CLK='1') THEN IF Q<9300 THEN Q<=Q+1; Good luck

ro888, ERROR:Xst:1831 - Missing ports are:DOA0 DIA0 ERROR:Xst:1832 - Unknown ports are:DOA DIA Maybe it helps when you change the signals DOA to DOA0 and DIA to DIA0 ? Blacktom

Hello Bandgap, I think i found something what the problem is. The fault is in the following piece of the code SIGNAL wire: BIT_VECTOR(3 DOWNTO 0); fai: FOR i IN 15 DOWNTO 1 GENERATE mux0i: mux2to1 GENERIC MAP(one_delay) PORT MAP(IN2(i), IN2_int(i), SEL(3), IN2_int(i)); wire((i+1)*4-1 DOWNTO...

Hello Bandgap, One question, how does the port map of the component mux4bit looks like?