Tek-Tips is the largest IT community on the Internet today!

Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!

  • Congratulations dencom on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!

Recent content by jackseiko

  1. jackseiko

    What's wrong witht that code?

    Hi Bert, thank you so much for your reply, I have made the change, but I still encounter with the same problem which is; ERROR:HDLParsers:808 - "C:/XilinX92i/transmitter/switches.vhd" Line 24. = can not have such operands in this context. I couldn't get what's the problem with that code. I...
  2. jackseiko

    OBUFDS or OBUFDS_LVDS ?? plz help me about differential signal

    thank you so much, it really helps :)
  3. jackseiko

    What's wrong witht that code?

    someone please tell me what's the problem with the code? TAI ------------------------------------------------------------ entity switches is port( clock : in std_logic; Switches : in std_logic_vector ( 3 downto 0); output: out std_logic_vector (7 downto 0) ); end switches; architecture...
  4. jackseiko

    OBUFDS or OBUFDS_LVDS ?? plz help me about differential signal

    hi, I need to use [LVDS(350 mV)] differential signal input/output at my project . But I have no experience about using differential signal, do I need to use OBUFDS or OBUFDS_LVDS component ??? I'd be grateful if u give me very little example of usage of this components. Thanks in advance...
  5. jackseiko

    VHDL - synthesized error, please help me out!!

    hi, when the code is synthesized, I got the error below: ERROR:Xst:827 - "C:/Xilinx92i/timer.vhd" line 19: Signal cntr cannot be synthesized, bad synchronous description. would you please check my short code and tell me why do I encounter such a error ? thanks in advance...

Part and Inventory Search

Back
Top