Tek-Tips is the largest IT community on the Internet today!
Members share and learn making Tek-Tips Forums the best source of peer-reviewed technical information on the Internet!
-
Congratulations strongm on being selected by the Tek-Tips community for having the most helpful posts in the forums last week. Way to Go!
why 32bit kernel support more than 4GB mem
- Thread starter guelph
- Start date
Hi
I heard 32 bit kernel cant'support more than 4gb physical memory , Inotherwords you should go to 64bit for >4gb memory for sparc and p-series hardware arch..
But Intel systems of 32 bit, can support >4gb real memory..
with segementation model concept.
sushveer
IBM certified specialist-p-series AIX5L System Administration
AIX/SOLARIS/WEBSPHERE-MQ/TIVOLI Administrator
I heard 32 bit kernel cant'support more than 4gb physical memory , Inotherwords you should go to 64bit for >4gb memory for sparc and p-series hardware arch..
But Intel systems of 32 bit, can support >4gb real memory..
with segementation model concept.
sushveer
IBM certified specialist-p-series AIX5L System Administration
AIX/SOLARIS/WEBSPHERE-MQ/TIVOLI Administrator
hello,
there's a "trick"
)
first , consider a 32 bit adress : eg 0x2FFF FFFF.
This kind of address is used by applications, and an application can not adress more thn 4GB of memory (2^32).
The kernel has a broader range of adress space. Before to go on, keep in mind, that AIX kernel organizes memory in segments (max of more than 16 M segments, ie 2^24, in 32 bit mode), and each segment is made of 65536 pages of 4 kb (ie 256 MB).
A process will own 16 segments of 256 MB), therefore 4 GB.
So from the kernel point of view, this adress is made of several components :
The first 4 bits (ie "2") in fact point to a register which has a lenght of 24 bits, and point to a segment number.
The following 16 bits of the adress point to the page in the segment which contain the information.
And the remaining 12 bits of the adress point to the byte in the page which has the information.
Therefore The effective adress (32 bits as 0x2FFF FFFF) is translated to a 52 bits adres because the frst 4 bits of the effective adress point to a 24 bit register).
Honestly, I don't see the link with the 96 GB RAM limit, there are still mechanisms after this to translate the 52 bits virtuals adress to a physical adress, and at this step I lost the trail(
regards
there's a "trick"
)first , consider a 32 bit adress : eg 0x2FFF FFFF.
This kind of address is used by applications, and an application can not adress more thn 4GB of memory (2^32).
The kernel has a broader range of adress space. Before to go on, keep in mind, that AIX kernel organizes memory in segments (max of more than 16 M segments, ie 2^24, in 32 bit mode), and each segment is made of 65536 pages of 4 kb (ie 256 MB).
A process will own 16 segments of 256 MB), therefore 4 GB.
So from the kernel point of view, this adress is made of several components :
The first 4 bits (ie "2") in fact point to a register which has a lenght of 24 bits, and point to a segment number.
The following 16 bits of the adress point to the page in the segment which contain the information.
And the remaining 12 bits of the adress point to the byte in the page which has the information.
Therefore The effective adress (32 bits as 0x2FFF FFFF) is translated to a 52 bits adres because the frst 4 bits of the effective adress point to a 24 bit register).
Honestly, I don't see the link with the 96 GB RAM limit, there are still mechanisms after this to translate the 52 bits virtuals adress to a physical adress, and at this step I lost the trail
(regards
- Status
Similar threads
