Hey, I am a beginner in VHDL, and I have a question, can anyone please help me?
I need to write a VHDL code for a carry ripple adder of 4bit, but I don’t know what’s the difference between the structural mode like the one below, and the direct addition (c <= a + b where a,b,c are 4 bit long.
The maximum combinational path delay of RCA_nbit is: 13.902ns
Whereas for the direct adding is: 10.531ns.
So, why should I use the structural mode, if the direct adding has less delay?
And if I wanted to implement this code on FPGA, which code should I use (the structural or the direct adding) ?
entity RCA_nbit is --Ripple Carry Adder - n bit
GENERIC(n: INTEGER := 4);
Port ( a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
cin : in STD_LOGIC;
clk : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (n-1 downto 0);
cout : out STD_LOGIC);
end RCA_nbit;
architecture Behavioral of RCA_nbit is
COMPONENT FullAdder is port (a,b,cin,clk : in STD_LOGIC; sum, cout : out STD_LOGIC);
end component;
signal t: STD_LOGIC_VECTOR (n downto 0);
begin
t(0) <= cin; cout <= t;
FA: for i in 0 to n-1 generate
FA_i: FullAdder port map (a(i),b(i),t(i),clk,sum(i),t(i+1));
end generate;
end Behavioral;
I need to write a VHDL code for a carry ripple adder of 4bit, but I don’t know what’s the difference between the structural mode like the one below, and the direct addition (c <= a + b where a,b,c are 4 bit long.
The maximum combinational path delay of RCA_nbit is: 13.902ns
Whereas for the direct adding is: 10.531ns.
So, why should I use the structural mode, if the direct adding has less delay?
And if I wanted to implement this code on FPGA, which code should I use (the structural or the direct adding) ?
entity RCA_nbit is --Ripple Carry Adder - n bit
GENERIC(n: INTEGER := 4);
Port ( a : in STD_LOGIC_VECTOR (n-1 downto 0);
b : in STD_LOGIC_VECTOR (n-1 downto 0);
cin : in STD_LOGIC;
clk : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (n-1 downto 0);
cout : out STD_LOGIC);
end RCA_nbit;
architecture Behavioral of RCA_nbit is
COMPONENT FullAdder is port (a,b,cin,clk : in STD_LOGIC; sum, cout : out STD_LOGIC);
end component;
signal t: STD_LOGIC_VECTOR (n downto 0);
begin
t(0) <= cin; cout <= t;
FA: for i in 0 to n-1 generate
FA_i: FullAdder port map (a(i),b(i),t(i),clk,sum(i),t(i+1));
end generate;
end Behavioral;