I have seen so many definitions, and all of them wrong, that I wonder what exactly is being taught at schools around the world.
IRQ=Interrupt Request Queue
It is a software stack where all interrupts are queued for processing, usually by the I/O, but sometimes with processor intervention.
On the old Interrupt Buss there were 16 physically unique interrupt request lines [IRL's]. However, because most systems were 4x4, four Input/Output Modules [IOM's] and four central processing modules [CPM's], this resulted in 64 physically unique, separate, and simultaneously accessible interrupts.
Intel and AMD have come up with a lot of schemes, but even the latest PCI-X is lame, using 16 interrupts, with 4 additional for control.
So, your interrupts are 0-15, and neither Intel nor AMD have ever gotten around to what was intended, 64 interrupts that are physically unique and accessible simultaneously.
Secondly, neither Intel nor AMD know what the acronum IRQ means. They keep referring to it as if this was the interrupt buss, it is not, it is a stack within the IOCB [Input/Output Control Block].
And a stack is data, not hardware.
When you try to equate hardware to software, there are problems.
Plug and Play uses the programmable interrupt controller [PIC] and the Advanced Programmable Interrupt Controller [APIC] to route and translate interrupt requests for devices back and forth from the I/O to such devices. As such, PIC and APIC are Host Controllers.
The PCI Controller is actually the PCI Host Controller and the SCSI Controller is actually the SCSI Host Controller. Both devices between the I/O and the peripherals [devices].
The "port" is an offset address to the IOCW [Input/Output Control Word] which is the same as the IOCB.
The IOCB is the block that is on the stack for every Interrupt Request in the Interrupt Request Queue.
These can build to easily 100,000 IRQ's and more.
But the real problem with all devices and drivers is not the IRQ nor the IRL, it is the complete misunderstanding of how interrupts are supposed to be generated and handled, and the false assumption that modern computers can accomplish management of interrupts with software emulation.
Obviously, if you cannot access the APIC to set the Interrupt Number, but are left at the mercy of software developers who have no idea of how interrupts work, neither the software nor the device is going to work.
Add to that each device now is starting to have its own controller, it's own APIC complete with its own BIOS and the confusion becomes a nightmare for adding a simple device, such as a DVD.
For all the professors and Intel and AMD's engineers: go look up the design of mainframe interrupts and the interrupt buss and interrupt handling, you've got it all wrong.
from the designer of interrupt busses long before the PC existed.
IRQ=Interrupt Request Queue
It is a software stack where all interrupts are queued for processing, usually by the I/O, but sometimes with processor intervention.
On the old Interrupt Buss there were 16 physically unique interrupt request lines [IRL's]. However, because most systems were 4x4, four Input/Output Modules [IOM's] and four central processing modules [CPM's], this resulted in 64 physically unique, separate, and simultaneously accessible interrupts.
Intel and AMD have come up with a lot of schemes, but even the latest PCI-X is lame, using 16 interrupts, with 4 additional for control.
So, your interrupts are 0-15, and neither Intel nor AMD have ever gotten around to what was intended, 64 interrupts that are physically unique and accessible simultaneously.
Secondly, neither Intel nor AMD know what the acronum IRQ means. They keep referring to it as if this was the interrupt buss, it is not, it is a stack within the IOCB [Input/Output Control Block].
And a stack is data, not hardware.
When you try to equate hardware to software, there are problems.
Plug and Play uses the programmable interrupt controller [PIC] and the Advanced Programmable Interrupt Controller [APIC] to route and translate interrupt requests for devices back and forth from the I/O to such devices. As such, PIC and APIC are Host Controllers.
The PCI Controller is actually the PCI Host Controller and the SCSI Controller is actually the SCSI Host Controller. Both devices between the I/O and the peripherals [devices].
The "port" is an offset address to the IOCW [Input/Output Control Word] which is the same as the IOCB.
The IOCB is the block that is on the stack for every Interrupt Request in the Interrupt Request Queue.
These can build to easily 100,000 IRQ's and more.
But the real problem with all devices and drivers is not the IRQ nor the IRL, it is the complete misunderstanding of how interrupts are supposed to be generated and handled, and the false assumption that modern computers can accomplish management of interrupts with software emulation.
Obviously, if you cannot access the APIC to set the Interrupt Number, but are left at the mercy of software developers who have no idea of how interrupts work, neither the software nor the device is going to work.
Add to that each device now is starting to have its own controller, it's own APIC complete with its own BIOS and the confusion becomes a nightmare for adding a simple device, such as a DVD.
For all the professors and Intel and AMD's engineers: go look up the design of mainframe interrupts and the interrupt buss and interrupt handling, you've got it all wrong.
from the designer of interrupt busses long before the PC existed.