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weird exam question

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twistadias

twistadias

Technical User
Jun 25, 2009
1
NZ
Got my exams in two days and this question has come up in the last 3 exams.

How should a proceudure in VHDL be described in order to be synthesizeable?

Im guessing that there should be at least 1 input parameter.

Professor hinted that it might be in this exam too and the exams in 2 days. Any help would be greatly appreciated.
 
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