edhunter2003
Technical User
Hi,
When I try to synthesise a vhdl module, I get the following warnings.
I understand that this can happen if I assign values to a signal, but is never used as an assignment to other signals. The thing is, this happens on every signal in my design, even on ones that I know are used as assignments. For the inputs I get the following warning.
I am using Xilinx ISE 5.2i. Anybody have any idea why this is happening? It doesn't happen with other modules I have.
Thanks all,
Ed
When I try to synthesise a vhdl module, I get the following warnings.
Code:
WARNING:Xst:646 - Signal <catcheckval4> is assigned but never used.
I understand that this can happen if I assign values to a signal, but is never used as an assignment to other signals. The thing is, this happens on every signal in my design, even on ones that I know are used as assignments. For the inputs I get the following warning.
Code:
WARNING:Xst:647 - Input <zrl<0>> is never used.[\code]
Then, if I ignore these warnings and do a translate on the design, I get the following error (I don't know if the two are connected).
[code]FATAL_ERROR:NgdBuild:basnbmain.c:1910:1.71.4.1 - Design is empty. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at [URL unfurl="true"]http://support.xilinx.com.[/URL] If you need further assistance, please open a Webcase by clicking on the "WebCase" link at [URL unfurl="true"]http://support.xilinx.com[/URL]
I am using Xilinx ISE 5.2i. Anybody have any idea why this is happening? It doesn't happen with other modules I have.
Thanks all,
Ed