Warning: Signal <> is assigned but never used.

[elin05]

I'm new to VHDL and could use some help. I'm getting the "Warning: Signal <reset_default> is assigned but never used." Can I fix this without adding another port to my entity?

Thanks
Eric

Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity waveform is
Port ( waveform_rst : in STD_LOGIC;
waveform_signal1 : out STD_LOGIC;
waveform_signal2 : out STD_LOGIC;
waveform_signal3 : out STD_LOGIC;
waveform_signal4 : out STD_LOGIC;
waveform_signal5 : out STD_LOGIC);
end waveform;

architecture Behavioral of waveform is
signal reset_default : std_logic := '0';
begin

process (waveform_rst)
begin

reset_default <= waveform_rst;
if reset_default = '0' then
waveform_signal1 <= '0',
'1' after 1us,
'0' after 2us,
'1' after 3us,
'0' after 4us,
'1' after 5us;

waveform_signal2 <= '0',
'1' after 2us,
'0' after 4us,
'1' after 6us,
'0' after 8us,
'1' after 10us;

waveform_signal3 <= '0',
'1' after 3us,
'0' after 6us,
'1' after 9us,
'0' after 12us,
'1' after 15us;

waveform_signal4 <= '0',
'1' after 4us,
'0' after 8us,
'1' after 12us,
'0' after 16us,
'1' after 20us;

waveform_signal5 <= '0',
'1' after 5us,
'0' after 10us,
'1' after 15us,
'0' after 20us,
'1' after 25us;

end if;
end process;
end Behavioral;