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wait statements dont work with synthesis tool

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jsmokey

Technical User
Aug 19, 2005
10
US
Hi,
I created a vhdl that simulates correctly. However i used "wait for x ns" statements in the process with no sensitivity list. when i tried to synthesize this using the tool, it says there is an error because the fpga doesnt recognize wait for statements. I decided to use a counter that is in another process that gets incremented every time a clock rising edge from the testbench is sent to the main file. The only problem is that i need this to have some sort of wait in order to take the time for the result to be correct. An example of this is:

a <= b + c;
wait for 2 ns;
x <= a;
etc...

to replace the wait statement i tried to use a counter that i reset right before a while loop but this does not work. Can anyone tell me why this doesnt work?

--im using this to control the counter

process(externalclk)
begin
if externalclk'event and externalclk = 1 then
loopcounter <= loopcounter + 1;
end if;
end process;

--then in the main process im doing this to try to replace the wait for statements with something like this
a<= b+c;
loopcounter <= 0; --reset this because another process is incrementing it so start it at zero again
while loopcounter < 2 loop --just a dummy while loop to replace the 2 ns wait
end loop;
x <= a;

Ive tried to fix this numerous ways but i cant seem to come up with the solution to this one...can anyone help with this? Thanks


 
hi,
i think i while loop cannot be synthesized too.

maybe u can use
if counter = 2 then
x <= a;
end if;

but i'm not sure ..
chris
 
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