wait for

[Nilak]

I am making an LCD interface, and for the initialization part, several signals must be delayed over some time. How can I go about incorporating the "wait for" statement so that I can delay the first several signals when initializing? Any help would be greatly appreciated.

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-- POWER-ON => 38H => 38H => 06H => 0EH => 01H => END OF INI => 80H --
-- CLK Ts >15ms >4.1ms >40us >40us >40us >1.64ms >40us -- --
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-

 

[adithyay]

If you are just looking for the usage of wait look at the text below the dashed line.

If you are wondering why ur wait statement is not getting synthesised, some synthesis tools do not support synthesis of wait statement.

Other alternative that can be suggested is use of 'after', but some tools might not synthesis 'after'. Usually one of the two should be synthesisable.

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wait statement Cause execution of sequential statements to wait.

[ label: ] wait [ sensitivity clause ] [ condition clause ] ;

wait for 10 ns; -- timeout clause, specific time delay.
wait until clk='1'; -- condition clause, Boolean condition
wait until A>B and S1 or S2; -- condition clause, Boolean condition
wait on sig1, sig2; -- sensitivity clause, any event on any
-- signal terminates wait

 

[Nilak]

Because I'm acustomed to using a sensitivity list in a process, I used a counter to simulate a delay. Which is the more efficient method for implementing a delay at startup? Thank you for your reply but the problem I was having is figuring out where exactly these statement can be placed. Can they be placed outside a process? Can a process have a sensitivity list of some signals and a "wait" statement for others? I have a feeling these statement may not be synthesizable although I am using the Xilinx ISE Webpack 7.

 

[adithya1]

The Wait statement can be used where ever u have sequential statements. it just creates delay between 2 sequentially executing statements. So it can be inside or outside a process where ever u want it to get the work done.

I guess using counters is a fairly good idea. As long as gets the work done with minimial wastage of cells.

I remember using Wait/after one of the two with Xilinx ISE. i dont remember which one is synthesizable.

Here is a set of examples using wait, i hope this helps.
-----------------------------------------------------------
wait for <specific time>;
STIMULUS: process
begin
SEL <= '0';
BUS_B <= "0000";
BUS_A <= "1111";
wait for 10 ns; // recalling the process after 10ns
SEL <= '1';
wait for 10 ns;
-- etc, etc
end process STIMULUS;

wait on <signal list>;

process
begin
if (A='1' or B='1') then
Z <= '1';
else
Z <= '0';
end if;
wait on A, B; // wait on the events
end process;

wait until <condition>;

process
begin
wait until CLK='1'; // wait until condition
Q <= D;
end process;

wait;

STIMULUS: process
begin
SEL <= '0';
BUS_B <= "0000";
BUS_A <= "1111";
wait for 10 ns;
SEL <= '1';
wait; // suspends forever
end process STIMULUS;

 

[Nilak]

Thanks for the help.