wait for statement inside a process

[carbon9]

Hi all,

I've trying to simulate a simple state machine with VHDL code below:

library ieee;
use ieee.std_logic_1164.all;

entity p82 is

	port(a, c, clk, rst: in std_logic;
		 x: out std_logic);
end p82;

architecture behavior of p82 is
		
type state is (stateA, stateB);
signal pr_state, nx_state: state;

begin

-----Lower Section--------

	process(rst, clk)
	begin
		if(rst='1') then
			pr_state<=stateA;
		elsif(clk'event and clk='1') then
			pr_state<=nx_state;
		end if;
	end process;

---Upper Section----------

	process(a, c, pr_state)
	begin
		
		case pr_state is
			
			when stateA =>
				x<=a;
				wait for 10ns;-->ERROR
				x<=c;
				nx_state<=stateB;
							
			when stateB =>
				x<=c;
				wait for 10ns;--->ERROR
				x<=a;
				nx_state<=stateA;
		
		end case;
	
	end process;

end behavior;

But, the compiler gives error: "A wait statement is illegal for a process with a sensitivity list." But I need to make delays on those points. How can I solve this problem?

Regards

 

[bonami172]

Hi,
You can't use the "wait for" in state machine design.
For making delays, you can define the new states. The number of new states depend on your clock frequency. For example, if your frequency is 10ns , you need one new state for delay 10ns.