VHDL 1

[Hasan22]

Well ; I need to created a data generator to send packets ( as Start bits,Header,Data,Parity,Checksum,)I use a 50MHZ divided to 4Hz clock ; Can anyone tell me how to star to write this type of a generator please

I need to send 1010 as the Start bit
and an 8 bit string as the header
24 bit data
4 bit parity
8 bit check

How do i select inputs and outputs and signals ?
Do I have to use a finite state machine here ?
I would be glad if someone can give me an idea or sample code for the above

Thanks!

 

[rappinglove]

Hi Hasan how are you getting on now?
I would say you do not have to use a FSM here but it would make things much easier and the readability would be improved. you can then use FSM as a controller.

good luck.