VHDL - synthesized error, please help me out!!

[jackseiko]

hi, when the code is synthesized, I got the error below:

ERROR:Xst:827 - "C:/Xilinx92i/timer.vhd" line 19: Signal cntr cannot be synthesized, bad synchronous description.

would you please check my short code and tell me why do I encounter such a error ? thanks in advance

-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity timer_alti is
port( clk: in std_logic;
reset: in std_logic;
timer_alti : out std_logic
);

end timer_alti;

architecture timer_alti of timer_alti is
signal cntr: integer range 0 to 3200;
begin
process(clk, reset)
begin
cntr <= 0;
if (reset='1') then
cntr <=0;
elsif (clk'event and clk='1') then
cntr <= cntr + 1;
end if;

if(cntr=3200) then
timer_alti <='1';
cntr <=0 ;
end if;
end process;


end timer_alti;

 

[m4xp0wer]

Try this:

process(clk, reset)
begin

if (reset='1') then
cntr <=0;
timer_alti<='0';
elsif (clk'event and clk='1') then
cntr <= cntr + 1;
if(cntr=3200) then
timer_alti <='1';
cntr <=0 ;
else
timer_alti<='0';
end if;
end if;


end process;