VHDL synthesis problem

[brumbarchris]

Hi all, I have written a small piece of code in an attemt of learining VHDL. The code is a first step in the implementation of a UART transmitter. The code compiles and simulates OK, but when I try to implement the design (using the webpack from XILINX, for a CoolRunnerII CPLD), I get the following error:

ERROR:Xst:827 - "D:/Xilinx/MyProjects/UART_Transmitter/UART_Transmitter.vhd" line 46: Signal state cannot be synthesized, bad synchronous description.
-->


So here is my code(only the architectural description):


architecture Behavioral of UART_Transmitter is

signal state :STD_LOGIC:='0';

begin
process(clock_in,data_in,state)
variable index :natural:=0;


begin
if data_in'event then
state<='1';
end if;

if state='1' then if clock_in='1' and clock_in'event then
data_out<=data_in(index);
index:=index+1;
if index=8 then
index:=0;
state<='0';
end if;
end if;
end if;

end process;
end Behavioral;