VHDL Programming Error help

[srikki9]

Hi
I have experienced the following error in the below attached code,

"Bounds of non-constant index addressing array reaches beyond the bounds of array" on line 131.(I have labelled line 131 in the below code).

I think it refers to the statement where i have used a variable "delay_val" as an index of the array "internal_reg". I have declared the variable "delay_val" and according to the code, it does not go beyond the maximum value of the register,"10".

I cannot understand why i am still getting this error. Please help.

CODE
----

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity test is
port(clock,reset,enable : in std_logic;
len : in std_logic_vector(0 to 1);
seq_num : in std_logic_vector(2 downto 0);
output : out std_logic;
delay_output,end_of_sequence : out std_logic;
edge_counter,delay,num_sequence,test5 : out integer
);
end test;

architecture behavioural of test is

signal new_bit: std_logic;
signal internal_reg: std_logic_vector(10 downto 0); "SIZE OF REGISTER = 11"
signal internal_reg_next: std_logic_vector(10 downto 0);
signal seq_indicator,new_seq: std_logic;

begin

code_gen: process(clock,reset)

variable count: integer;
variable delay_val: integer;
variable seq_val: integer;
variable code_length: integer;
variable num_seq: integer;
variable x: integer;

begin

edge_counter <= count;
delay <= delay_val;
end_of_sequence <= seq_indicator;
num_sequence <= seq_val;
test5 <= x;

case seq_num is

when &quot;000&quot; => num_seq := 50; when &quot;001&quot; => num_seq := 100; when &quot;010&quot; => num_seq := 150;
when &quot;011&quot; => num_seq := 200; when &quot;100&quot; => num_seq := 250; when &quot;101&quot; => num_seq := 300;
when &quot;110&quot; => num_seq := 350; when others => num_seq := 400;

end case;

case len is

when &quot;00&quot; =>

-- XOR bits 6,5,2,1
code_length := 64;
new_bit <= internal_reg(5) xor internal_reg(4);
output <= internal_reg(0);
internal_reg_next <= internal_reg(9 downto 0) & new_bit;

when &quot;01&quot; =>

-- XOR bits 7,6
code_length := 128;
new_bit <= internal_reg(6) xor internal_reg(5);
output <= internal_reg(0);
internal_reg_next <= internal_reg(9 downto 0) & new_bit;

when &quot;10&quot; =>
-- XOR bits 8, 4, 3, and 2
code_length := 256;
new_bit <= internal_reg(7) xor internal_reg(5) xor internal_reg(4) xor internal_reg(3);
output <= internal_reg(0);
internal_reg_next <= internal_reg(9 downto 0) & new_bit;

when OTHERS =>

--XOR bits 9,6,4,3
code_length := 512;
new_bit <= internal_reg(8) xor internal_reg(4);
output <= internal_reg(0);
internal_reg_next <= internal_reg(9 downto 0) & new_bit;

end case;


if (reset = '1') then
internal_reg <= (3 => '1', OTHERS => '0');
count := 0;
delay_val := 1;
seq_indicator <= '0';
seq_val := 0;

elsif (clock'EVENT AND clock ='1') then

if(enable = '1') then &quot; LINE 131&quot;
count := count+1;
internal_reg <= internal_reg_next;
delay_output <= internal_reg(delay_val); &quot;PROBABLE ERROR LOCATION&quot;
x:=(code_length*(seq_val+1));


if (count = x) then
seq_val := seq_val+1;
seq_indicator <= '1';
else seq_indicator <= '0';
end if;

if (seq_val = num_seq) then count := 0;
delay_val := delay_val+1;
seq_val := 0;
end if;

if (delay_val = 8) &quot;delay_val&quot; DOES NOT INCREASE TO MORE THAN 8 ACCORDING TO THIS LINE
delay_val := 1;
end if;

end if;
end if;
end process;
end behavioural;

 

[RVSachin]

I didn't face any error of the kind you have mentioned. I did, however, see some errors which was basically syntax errors, and few warnings due to incomplete sensitivity list.
Your design mapped just fine otherwise.

Here's the code I have synthesized:
--__________________________________________

architecture behavioural of test is

signal new_bit: std_logic;
signal internal_reg: std_logic_vector(10 downto 0); -- &quot;SIZE OF REGISTER = 11&quot;
signal internal_reg_next: std_logic_vector(10 downto 0);
signal seq_indicator,new_seq: std_logic;

begin

code_gen: process(clock,reset, seq_num, len, seq_indicator, internal_reg)

variable count: integer;
variable delay_val: integer;
variable seq_val: integer;
variable code_length: integer;
variable num_seq: integer;
variable x: integer;

begin

edge_counter <= count;
delay <= delay_val;
end_of_sequence <= seq_indicator;
num_sequence <= seq_val;
test5 <= x;

case seq_num is

when &quot;000&quot; => num_seq := 50; when &quot;001&quot; => num_seq := 100; when &quot;010&quot; => num_seq := 150;
when &quot;011&quot; => num_seq := 200; when &quot;100&quot; => num_seq := 250; when &quot;101&quot; => num_seq := 300;
when &quot;110&quot; => num_seq := 350; when others => num_seq := 400;

end case;

case len is

when &quot;00&quot; =>

-- XOR bits 6,5,2,1
code_length := 64;
new_bit <= internal_reg(5) xor internal_reg(4);
output <= internal_reg(0);
internal_reg_next <= internal_reg(9 downto 0) & new_bit;

when &quot;01&quot; =>

-- XOR bits 7,6
code_length := 128;
new_bit <= internal_reg(6) xor internal_reg(5);
output <= internal_reg(0);
internal_reg_next <= internal_reg(9 downto 0) & new_bit;

when &quot;10&quot; =>
-- XOR bits 8, 4, 3, and 2
code_length := 256;
new_bit <= internal_reg(7) xor internal_reg(5) xor internal_reg(4) xor internal_reg(3);
output <= internal_reg(0);
internal_reg_next <= internal_reg(9 downto 0) & new_bit;

when OTHERS =>

--XOR bits 9,6,4,3
code_length := 512;
new_bit <= internal_reg(8) xor internal_reg(4);
output <= internal_reg(0);
internal_reg_next <= internal_reg(9 downto 0) & new_bit;

end case;


if (reset = '1') then
internal_reg <= (3 => '1', OTHERS => '0');
count := 0;
delay_val := 1;
seq_indicator <= '0';
seq_val := 0;

elsif (clock'EVENT AND clock ='1') then

if(enable = '1') then -- &quot; LINE 131&quot;
count := count+1;
internal_reg <= internal_reg_next;
delay_output <= internal_reg(delay_val); --&quot;PROBABLE ERROR LOCATION&quot;
x:=(code_length*(seq_val+1));


if (count = x) then
seq_val := seq_val+1;
seq_indicator <= '1';
else seq_indicator <= '0';
end if;

if (seq_val = num_seq) then count := 0;
delay_val := delay_val+1;
seq_val := 0;
end if;

if (delay_val = 8) then -- &quot;delay_val&quot; DOES NOT INCREASE TO MORE THAN 8 ACCORDING TO THIS LINE
delay_val := 1;
end if;

end if;
end if;
end process;
end behavioural;
--_________________________________________

 

[srikki9]

Thanks Sachin. I am actually new to writing VHDL codes. What is the difference between simulating a code and synthesizing a code ? I actually simulated this code and found the errors i mentioned. I simulated using the Altera Maxplus II software. Do i need to use a synthesis tool myself?
Where does synthesis come into the picture ? I thought the steps towards programming a PLD includes:
(1) writing the code
(2) checking for errors
(3) compile it using your device of interest
(4) simulate the code using a vector file
(5) program the device.

Where does synthesis come in this step list? would really appreciate if you could give me a little more details.
Thanks
Raghu

 

[RVSachin]

Simulation: Verification -Checking for whether the code works fuctionally

Synthesis: Generating netlist.

Note that, not all that can be simulated, can, necessarily, be synthesized

In your case, when u say COMPILE, you are synthesizing it.

 

[srikki9]

Hi

Then, why is it that, when i compile and simulate , i get errors when you do not, when you synthesize it ? Could you tell me what tool you are using to synthesize ?

I have been using the Maxplus II baseline 10.2 software developed by altera. Are you using the same tool ? I have, in fact, tried to use the Maxplus Advanced Synthesizer. But, i could not understand how to use the generated .edf and .acf files to simulate my code after synthesizing. Have you used this software before ? If yes, then could you help me out on this ?

Thanks

Raghu

 

[RVSachin]

..No, I don't have Max+Plus II. I have Altera's Quartus. Compilers in both should be same, since both are from Altera.

The only thing is, I made minor changes to the code in terms of syntax and synthesized (...or in your terms, compiled ) it.

Did you check the code I have modified?

 

[srikki9]

Hi Sachin

I have made the changes but still get the same error message. I have tried all the devices i have using Maxplus II during the compilation. As you say, the compiler should be the same. So, have no idea why this is happening.

Can you think of anything else that could be the problem.

Thanks for your help.

Raghu


P.S. I was pretty sure the code runs well....but its so frustrating not to see the results. If this code runs on your machine....and if you ever get the time....could you simulate the code using the below .vec file and email me the .scf file ? A simulation time of about 500us would be enough. My email address: graghuvar007@yahoo.com.
If this is asking too much of you, ignore this . You have already helped me very much !!!


VECTOR FILE:

start 0;
stop 11000000;

interval 10;
inputs clock;
pattern
0 1;

inputs reset;
pattern
0000> 1
0030> 0;

RADIX DEC;

inputs enable;
pattern
0000> 0
0040> 1;

inputs len;
pattern
0> 0;

inputs seq_num;
pattern
0> 0;

outputs output;
outputs delay_output;
outputs edge_counter;
outputs delay;
outputs num_sequence;
outputs end_of_sequence;
outputs test5;

 

[srikki9]

Hi Sachin
I am having problems with my yahoo account. Just in case you decided to send the .scf file or have already sent it to the email address i had given, please send it to this new address: graghuvar9@yahoo.com

Sorry about this.
Thanks
Raghu