Vhdl process statement !

[Prab]

Hello: iam just a bit confused about how the vhdl process statement actually works...ne help would be appreciated...the problem is explained below:

process (clk,p_state,n_state)
begin
p_state <=RESET;
n_state <=READY;

if (Clk'EVENT and Clk = '1') THEN
Case present IS
WHEN RESET =>
COMMAND <= &quot;000000110010&quot;; -- Mode register
present<=WAITCLK;

WHEN PRECHARGE =>
COMMAND <= &quot;000000000000&quot;; -- Precharge allrows
present<=DESCISION;

END CASE;
ELSE
-- Do nothing.
END IF;
END Process;

Now once this process runs: p_state = reset is true therefore the first case statement is true...and it runs the command and sets p_state = waitclk, and then goes to the end of the process block ... but since p_state has changed (its in the sensetivity list) therefore the block is evaluated again...and at the start p_state = reset again...so if iam right then i can never leave the reset state...will always end up in it once the process is reevaluated.
PLS give some explanantion if you know i am wrong or if i am right.