VHDL problem with variables

[krkrkr]

Hello,
I've a problem when calling a procedure a passing variable to it, I tried my code in Quartus and compiled without errors but when I tried xilinx XPS which I have to use, I got the following error (undefined signal "aprio")
The code is down, any help???

architecture rtl of mylogic is

signal x : integer range 0 to 15 := 0;
signal y : integer range 0 to 15 := 0;

procedure add_prio (variable aprio: in integer;
variable aout: inout integer) is
begin
aout := aout + aprio;
end procedure add_prio;

begin

add_proc: process(clk) is
variable prio : integer range 0 to 15 :=0;
variable out : integer range 0 to 15 :=0;

if clk'event and clk = '1' then
prio := x;
add_prio(prio, out);
y <= out;
end if;
end process add_proc;

end rtl;