VHDL Package Port Mapping

[jackslap442]

I have created an 8 to 1 mux package. I now wish to use this package in another file but cant get the port mapping right. The package compiles without error and I have included the work library in the file in which i am using the package. Sample code below.

--Mux package
entity mux8t01
port(I :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Z :OUT STD_LOGIC);
end mux8t01
ARCHITECTURE behavior of mux8to1 is
BEGIN
WITH S SELECT
Z<=I(0) WHEN &quot;000&quot;
I(1) WHEN &quot;001&quot;
I(2) WHEN &quot;010&quot;
I(3) WHEN &quot;011&quot;
I(4) WHEN &quot;100&quot;
I(5) WHEN &quot;101&quot;
I(6) WHEN &quot;110&quot;
I(7) WHEN OTHERS
END behavior
.
.
package code....same ports as above
.
.

_____________________________________________________
--OTHER FILE TO USE PACKAGE
--work lib included
entity other
port(E,L,G,a1 :IN STD_LOGIC;
II :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
END other
ARCHITECTURE logic OF other IS
II(0)<=(E AND NOT a1) OR (G AND a1);
.
.
.similar logic forII(1)-II(7)
.
.
end logic
________________________________________________________
So, if someone could help me with the port mapping of the other file with the mux package i would be
thnx,
jackslap442

 

[farmerboy]

Have you tried to use this as a component? I think having this as a seperate .vhd file in the same project as your new code which you wish to write, and then port mapping this as component instantisation will work just cool!

 

[chinna24]

hi!
in u r package there are two inputs(I,S) AND ONE O/P Z
BUT IN U R MAIN PROGRAM U R NOT SUPPLYING TWO INPUTS SO THATS THE EORROR I GUESS....
AND ONE MORE THING IS U R PACKAGE RETUNRS 1 BIT OUT PUT BUT IN U R MAIN
PROGRAM ENTITY U TOOK OUT PUT AS 8 BIT VERCTOR...SO CHANGE THOSE THING AND GIVE A TRY...
MAKE SURE U INCLUDE THAT PACKAGE AS COMPONENT AND PORT MAP IT.
IF U HAVE ANY PROBLMES LET ME KNOW.