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VHDL Models
- Thread starter a3debut
- Start date
HosseinMoradi
Programmer
Dear a3debut
the only diffrence that they have is in synthesis.
for example some of instructions that are used for simulating can't be synthesised.EXP: blok and guarded in vhdl.
or power(**) function!!! you don't have any hardware that do this but you can use multiplier -first you should design it for synthesis-and model it.
Regarsd,
Hossein Moradi.
the only diffrence that they have is in synthesis.
for example some of instructions that are used for simulating can't be synthesised.EXP: blok and guarded in vhdl.
or power(**) function!!! you don't have any hardware that do this but you can use multiplier -first you should design it for synthesis-and model it.
Regarsd,
Hossein Moradi.
- Status