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VHDL latches

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kushan2001

kushan2001

Technical User
Jul 13, 2009
1
GB
Hi,

What is the best method for retaining the value of a signal created in one state of a FSM, into another state without inferring a latch ?

Thanx in advance..
 
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Hi Kushan,

Use a flip-flop. That's simply the best way to do it.

Bert
 
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