VHDL Fixed-point divider

[GSRUS]

Does anyone have the algorithm or VHDL code that
will implement a fixed-point divider?
In my case, I have two integer numbers.

numerator = 15-bit signed
denominator = 15-bit unsigned.

By construction, the magnitude of numerator will always be less than magnitude of denominator.

Ideally would like the results in Signed 15-bit decimal output format of 1.14 where the MSB is the sign bit, and
the 14 LSB is the fractional value (not remainder).
I will then add half scale to convert this to
an unsigned decimal format of 1.14

 

[senjed]

I'm pasting it from a PDF file which is available online at

http://www.engr.mun.ca/~theo/Courses/fm/pub/fm13sl.pdf

it's a psuedo code which could be written in VHDL very easily. I have written the VHDL code just form this, but I don't have it now.

/* do [q := a div b] by */ {
q = 0 ;
int e = b << N ;
int f = 0 ;
while( e != b ) {
e = e >> 1 ;
q = q << 1 ;
const int g = f + e ;
if( a >= g {
q = q | 1 ;
f = g ; } } }