VHDL - Driving 1 bit off 2 clocks

[snooks911]

I am working on implementing the MC6850 ACIA for academic purposes. The implementation requires that when data is written to the data register, the empty flag is set to zero and when the data is read from the register, it is set to 1 (to indicate empty).

The reading and writing are 2 different processes and I am not allowed to modify this same empty bit by 2 different processes. I am not sure how exactly to set this bit properly. Would somebody here be able to provide any advice? I'd really appreciate it.

Thank you,

Snooks

 

[BertVhdl]

Hi Snooks,

You should use flags between processes. The implementation of such inter process communication, depents very much on the specific demands.

I wrote an example below, to give you an idea of how to do this.

[codewrite data process]
process(clk) is
begin

if( clk'event AND clk = '1' ) then

if( write_enable = '1' ) then

...Code to write the data...

write_flag <= '1';
else
write_flag <= '0';
end if;

end if;

end process;
[/code]

[coderead data process]
process(clk) is
begin

if( clk'event AND clk = '1' ) then

if( read_enable = '1' ) then

...Code to read the data...

read_flag <= '1';
else
read_flag <= '0';
end if;

end if;

end process;
[/code]

[codecontrol empty flag]
process(clk) is
begin

if( clk'event AND clk = '1' ) then

if( read_flag = '1' ) then
empty_flag <= '1';
els if( write_flag = '1' ) then
empty_flag <= '0';
end if;

end if;

end process;
[/code]

Hope this helps you a bit further!
Bert