VHDL DIVIDER SOURCE CODE QUESTION? I NEED EXPERT HELP

[ECE1ENGR]

I need some VHDL synthesis expert advise on the code given below. Someone please help me uncderstand exactly what is wrong with this code. I can synthesis it but when I download it to my FPGA board I doesn't perform as designed. Someone please help!!! I get no errors so its hard to tell exactly what is wrong


library IEEE;
library WORK;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Derricks_8x8_dividerWP is
Port ( DIVIDE : in STD_LOGIC;
DIVIDEN : in integer range 0 to 255;
DIVISOR : in integer range 0 to 100;
QUOTIENT : out integer range 0 to 255;
REMAINDER : out integer range 0 to 255);

end Derricks_8x8_dividerWP;

architecture Behavioral of Derricks_8x8_dividerWP is

signal calculated_quotient : integer range 0 to 64897;
signal base_div : integer range 1 to 256;
--signal new_calulated_quotient : integer range 0 to 255;
--signal REMAINDER1 : integer range 0 to 255;


begin
process (DIVIDE, calculated_quotient, divisor)

--variable base_div : integer range 1 to 256;
variable new_calulated_quotient : integer range 0 to 255;
variable REMAINDER1 : integer range 0 to 255;
variable i : integer range 0 to 255;
--variable load: std_logic;

begin

if (DIVIDE'EVENT AND DIVIDE = '1') THEN

REMAINDER1 :=0;
calculated_quotient <=0;
base_div <=1;
new_calulated_quotient :=0;
i := 0;

loop1: For i in 0 to 255 Loop

if (calculated_quotient < DIVIDEN) then

calculated_quotient <= base_div * DIVISOR;
base_div <= base_div + 1;
else exit;
end if;

if ( calculated_quotient <= dividen ) then

new_calulated_quotient := base_div - 1;
REMAINDER1 := DIVIDEN - calculated_quotient;
end if;

exit loop1 when (calculated_quotient >= DIVIDEN);
end loop loop1;
end if;

if (DIVIDE'EVENT AND DIVIDE = '0' AND calculated_quotient > DIVIDEN ) THEN

REMAINDER <= REMAINDER1;
QUOTIENT <= new_calulated_quotient;

end if;
end process;
end Behavioral;