richardian
Technical User
Hi Everyone. I am new to VHDL and am having a difficult time initializing a 544 bit register. The data type is std_logic_vector. Currently it is set to all '1's using the statement:
constant One544 : std_logic_vector(543 downto 0) := (others => '1');
I need to set the upper 32 bits to a unique pattern and the rest of the bits to '1'. How do I do this?
Regards,
Richard
constant One544 : std_logic_vector(543 downto 0) := (others => '1');
I need to set the upper 32 bits to a unique pattern and the rest of the bits to '1'. How do I do this?
Regards,
Richard