VHDL coding help

[srikki9]

Hi,

I am generating a 127-bit PN code using the following code: I just want to generate a trigger signal after every 127-bit sequence. So, basically, i count the positive edges of the clock after the PN code starts and then after the counter reaches 127, i generate the trigger signal. NOW, MY QUESTION HAS NOTHING TO DO WITH THE PN CODE. It is quite a simple one. When i simulate at low frequency like 1MHz, everything is fine. When i try to simulate at 25Mhz, the counter messes up. The "count" variable in the code increments from 0 to 120 then goes back to 0 and starts incrementing again.

I have seen this before. When you try to increment an integer variable, it always messes up at high frequencies.does all kinds of stupid things while incrementing. like once...it incremented until 49 and then it read 17 after that, etc etc. Am i doing something wrong ? Can't the PLD just do a simple thing as incrementing an integer variable properly ? There should nothing be wrong with the logic because it works perfectly at 1Mhz.

Is there a better alternative to a problem where you need to wait until a condition is reached to perform an action.

The PLD i am downloading the code into is an altera device EPF10K70RC240-4. I am using the ALtera Maxplus II Baseline software.

The code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity onlypn is

port( clock,reset,enable : in std_logic;
output,trigger : out std_logic;
counter : out integer
);
end onlypn;

architecture behavioural of onlypn is

signal new_bit: std_logic;
signal internal_reg: std_logic_vector(127 downto 0);
signal internal_reg_next: std_logic_vector(127 downto 0);

begin

code_gen: process(clock,reset,internal_reg,new_bit,enable)

variable count: integer;

begin

counter <= count;

new_bit <= internal_reg(6) xor internal_reg(5);
output <= internal_reg(0);
internal_reg_next <= internal_reg(126 downto 0) & new_bit;

if (reset = '1') then

internal_reg <= (3 => '1', OTHERS => '0');

elsif (clock'EVENT AND clock ='1') then

if(enable = '1') then
internal_reg <= internal_reg_next;
count := count +1;
if (count = 127) then
count := 0;
trigger <= '1';
else trigger <= '0';
end if;

end if;

end if;
end process;
end behavioural;


Thank you

 

[RVSachin]

Can you try constraining the variable COUNT with the required range?

It looks like you need to count only upto 127. So, declare COUNT as integer range 0 to 127. Otherwise, by default an integer type signal is assumed to be 32-bits wide bus.

Also, assignments for COUNT and TRIGGER under the reset condition are missing. These could be causing the problem.

 

[srikki9]

Thanks rvsachin. But, i have encountered this problem before too. Check out the following example.
In this example:

variable 'count' = counts the number of positive edges of clock.
variable 'seq_num' = counts the number of sequences ( 1 sequence = 128 bits/positive edges).
After 50 sequences, i have to increment the variable 'delay_val'. This process goes on until 'delay_val' reaches 8 when it has to be reset to 0.

This is what the code is doing. Now, when i simulate this code.... after seq_num reaches 49, it says constant there at 49 because the variable 'count' does not reach 128 after seq_num reaches 49. 'count' increments until 96 and then gets back to zero and the process goes on. The condition for 'seq_num' to increment is that count has to reach 128. Hence, 'seq_num' stays constant at 49. I have no idea why 'count' increments normally for 48 sequences and then stops working well after seq_num reaches 49.

I cannot spot a mistake in the code. I have tried to define 'count' in all possible cases just to be safe. But, apparently it still has a bug.Its highly possible that i might be missing something. I am still an amateur in VHDL coding. I willreally appreciate if you can help me on this.

CODE:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fixedlength is

port(clock,reset,enable : in std_logic;
output : out std_logic;
delay_output : out std_logic;
edge_counter,delay,num_sequence: out integer
);
end fixedlength;

architecture behavioural of fixedlength is

signal new_bit: std_logic;
signal internal_reg: std_logic_vector(10 downto 0);
signal internal_reg_next: std_logic_vector(10 downto 0);

begin

code_gen: process (clock,reset,internal_reg,new_bit)
variable count: integer range 0 to 520;
variable delay_val: integer range 0 to 8;
variable seq_val: integer range 0 to 55;

begin

edge_counter <= count;
delay <= delay_val;
num_sequence <= seq_val;

new_bit <= internal_reg(6) xor internal_reg(5);
output <= internal_reg(0);
delay_output <= internal_reg(0);
internal_reg_next <= internal_reg(9 downto 0) & new_bit;

if (reset = '1') then
internal_reg <= (3 => '1', OTHERS => '0');
count := 0;
delay_val := 0;
seq_val := 0;

elsif (clock'EVENT AND clock ='1') then

if(enable = '1') then
count := count+1;
internal_reg <= internal_reg_next;

if (count = 128) then
seq_val := seq_val+1;
count := 0;
else
count := count;
end if;

if (seq_val = 50) then
count := 0;
delay_val := delay_val+1;
seq_val := 0;
else
count := count;
end if;

if (delay_val = 8) then
delay_val := 0;
count := 0;
else
delay_val := delay_val;
count := count;
end if;
else
internal_reg <= (3 => '1', OTHERS => '0');
count := 0;
end if;
end if;
end process;
end behavioural;

 

[VHDLguy]

Firstly you say that this simulates at 1Mhz but not at 25Mhz. What exactly is your definition of simulate?

I am assuming that you actually mean that running on the target device at 25Mhz doesn't work, but at 1Mhz it does?
Because in theory there should be no simulation difference, unless you are simulating using a netlist with real delays etc.

If you are simulating using a syntheszed netlist with place and route delays etc then the problem may be that you simply didn't get the required speed, did the synthesis tool tell you what the worst path speed was?

What tools are you using for simulation and/or synthesis?

Finally (for now) my advice to new comers is - DON&quot;T USE VARIABLES. Other people will disagree, but I (and others) find that using variables (unless you are writting a behavioural model for testbenches etc) is the easiest way to make a mistake in an RTL design.

I notice that you did call your architecture behavioural, but you say you are targeting a PLD. So I assume that this is code actually going to the PLD, not test code that you are using to test another design and the use of the word behavioural has no real meaning?

 

[VHDLguy]

By the way,

Why is your internal_reg signal 128 bits in length?

You are only using 7 bits. Is the shift register around the wrong way?

 

[VHDLguy]

I tested your block exactly as written above.

I had problems with it not detecting when count = 127.
I fixed that by putting count := 0 in the reset condition.

However in most cases I really do not see why it would behave differently at 1 Mhz of 100000Ghz (if your simulator had that kind of resolution). See my earlier message.

I think you are asking why doesn't it work at 25Mhz in the PLD, not in simulation. Correct?

 

[RVSachin]

I tried simulating your code and found the behaviour to be OK (...although it could have been coded much more efficiently).
I can send you a snap-shot for this.

Can you let me know if I am missing something?

 

[srikki9]

Hi

Thank you for your responses. I have no problems with the code i put up the first time. I restricted the count variable to 127 and that solved the problem. Please look into the second piece of code i sent as a reply. In this code, even though i have initiated and restriced the count variable and defined its value in as many cases as possible, i am experiencing problems making it count normally. Check my response to rsachin's first reply where i have explained the behavior i am seeing in my simulation results.

So, i did not understand what code you were referring to in your replys. 'vhdlguy' seemed to respond to my first code which is solved. I am using MaxplusII Baseline version for design, compilation and simulation. I am using Maxplus Advanced synthesis tool for synthesis. About rvsachin's snapshot, again...are you referring to the second piece of code i sent ?

Thank you