VHDL code, what's wrong

[Howard123]

Hello,
The following code comes from the Altera web site. It indicates the implementation is incorrect. It seems to simulate OK. Can anyone tell me what's wrong with it?

ENTITY dff IS
PORT(
enable : IN BIT;
d, clk : IN BIT;
q : OUT BIT
);
END dff;

ARCHITECTURE maxpld OF dff IS
BEGIN
-- The following implementation is incorrect.
PROCESS(clk)
BEGIN
IF (clk'event AND clk = '1') THEN
IF (enable = '1' ) THEN
q <= d;
END IF;
END IF;
END PROCESS;
END maxpld;

Howard123

 

[jmxntg]

According to Altera's website:
"The section that is commented out uses the same logic, except the IF enable statement is switched. The commented section will not synthesize correctly in MAX+PLUS II because the enable input will feed both the enable on the flipflop and added combinatorial logic that then feeds the D input."

I don't have any idea about this.
Perhaps you should try to synthesize it on Quartus, since the website explicitly says that "...will not synthesize correctly in MAX+PLUS II".

Best regards,

jmxntg

 

[Howard123]

Thanks jmxntg,

It sounds like the code is OK, it's just the way it's simulated on Max Plus. I have tried Quartus II and the code simulates OK. Thanks again.

Howard