VHDL Bonus Homework Problem

[GregoriusBontrager]

I'm about ready to pull my hair out! For the following code:

library BITLIB;
use BITLIB.bit_apack.all;

entity COUNTER is
port (a, b, c, d: in bit; x, y, z: out bit);
end entity;
architecture COUNT of COUNTER is
signal na, nb, nc, nd: bit;
begin
na <= NOT a;
nb <= NOT b;
nc <= NOT c;
nd <= NOT d;
x <= a AND b AND c AND d;
y <= (na AND nb AND c AND d) OR (na AND b AND c) OR (na AND b AND d) OR (a AND nb AND d) OR (a AND nb AND c) OR (a AND b AND nc) OR (a AND b AND nd);
z <= (na AND nb AND nc AND d) OR (na AND nb AND c AND nd) OR (na AND b AND nc AND d) OR (na AND b AND c AND d) OR (a AND nb AND nc AND nd) OR (a AND nb AND c AND d) OR (a AND b AND nc AND d) OR (a AND b AND c AND nd);
end COUNT;

entity MEGACOUNTER is
port(A, B, C, D, E, F, G, H, I, J, K, L: in bit; number: out Integer);
end entity;
architecture MEGACOUNT of MEGACOUNTER is
component COUNTER
port (a, b, c, d: in bit; x, y, z: out bit);
end component;
signal R, S, T, U, V, W, X, Y, Z: bit;
begin
COUNT1: COUNTER port map (A, B, C, D, R, S, T);
COUNT2: COUNTER port map (E, F, G, H, U, V, W);
COUNT3: COUNTER port map (I, J, K, L, X, Y, Z);
number <= vec2int(R&S&T) + vec2int(U&V&W) + (X&Y&Z);
end MEGACOUNT;

I get the following compilation errors, all generated from the next-to-last line:

C0091: Indexed name vec2int must denote an array object
C0044: T is an unidentified identifier
C0091: Indexed name vec2int must denote an array object

I've been back and forth through my textbook for hours, and I can't for the life of me see what the problem is! Can anyone please help me ASAP?

Thanks,

Greg