VHDL bidirectional port questions

[John5788]

I am trying to design the Lattice CPLD: LC4032v to kind of act as a buffer for now, and am having problems dealing with the bidirectional ports.

I programmed the ports to direct data one way or another based on a clock. Here is a sample of what I am doing:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity OneToOne is
port (

-- Inputs
A0, A1: in std_logic;

-- Clocks
CLK0: in std_logic;

-- Outputs
B0, B1: out std_logic;

-- Bidirectional ports
A8, A9, B8, B9: inout std_logic);


end OneToOne;

architecture behavioral of OneToOne is
begin

B0 <= A0;
B1 <= A1;

process(CLK0)
begin

if(CLK0 = '0' AND CLK0'event) then
B8 <= A8;
B9 <= A9;

elsif(CLK0 = '1' AND CLK0'event) then
A8 <= B8;
A9 <= B9;

end if;

end process;

end behavioral;

However, when I test the waveform to see what it would do, the signals A8, A9, B8, B9 stay low and never accept values.

For example: CLK0 is 1, and B8 is 1, A8 remains 0 when it should be 1. Any help?

 

[jeandelfrigo]

John5788,

This is a funny experiment, at least I hope it is because I cannot see the use of this code.

For one thing I think this will give you timing issues when you want to implement this in real. Certainly at higher frequencies.

What I think is the problem is that you have the four flip flops in one process. I think there might be an issue with when the new signal values are assigned (allways at the end of the process.

I would suggest using two processes one for the rising edge flip flops and one for the falling edge flip flops.

regards,

jeandelfrigo