VHDL Asynchronous Reset Not Working!

[smcallis]

entity FIVEMHZ_TO_ONEMHZ is
port (A_Reset, CLKIN : in std_logic; Output : out std_logic);
end entity FIVEMHZ_TO_ONEMHZ;

architecture BEH of FIVEMHZ_TO_ONEMHZ is
signal A, B, C : std_logic;
begin
update : process (A_Reset, CLKIN)
begin
if A_Reset = '1' then
A <= '0'; B <= '0'; C <= '0';
elsif CLKIN = '1' and CLKIN'Event then
A <= ((not A) and (not B) and C);
B <= ((not A) and (not C));
C <= B;
end if;
end process update;

-- Generate Output
Output <= ((not A) and (not B) and (not C)) or (A and (not B) and (not C)) or (CLKIN and (not A) and B and (not C));

end architecture BEH;

This is a clock divider that takes an input clock, divides by five and then outputs a 50% duty cycle clock that's 1/5th the frequency. It simulates and synthesizes perfectly, then I put it on my chip (an XC9572XL CPLD) and it sits there doing nothingm, I can see the output go low when I hit the reset, then it goes high and just sits there, I've got a few other entities on the chip that take the reset, and it doesn't seem to work for them very well either, can anyone help with this?

 

[avib]

I can guess that the reset polarity is oposite (should be if A_Reset = '0' then)

Avi

 

[smcallis]

Actually, I found out there's a HUUUUUGGGGEEE bug in Xilinx ISE 7.1 wherein the JEDECs for several of their CPLDs aren't correctly generated, I applied a patch and it works fine now....grrrrr.