VHDL and Verilog using Sinplify

[aalbert]

Hi everybody !

I've got a problem using Sinplify, and my instructor can't help me !

I try to synthetise a project with a top VHDL file which uses 2 components.

The architecture of these components was synthetised in .vqm files (verilog quartus map) but when I synthetise the whole project, Sinplify creates 2 blackbox instead of the two components...

Do you know how to make sinplify using .vqm files for definition of components ?

Thanks in advance.


My architecture is like that :


Top component (vhdl file)
|
|
|
--------
| |
sub1 sub2 (vqm files)

 

[RVSachin]

Synplify outputs VQM files for the P&R tool.
It cannot take vqm file as input and so components corresponding to those vqm files are treated as black boxes.