VHDL Altera problem

[bbiandov]

Hi everyone,

I get a strange error when I try to compile a project which I KNOW used to compile just fine before. The source is coming out of a CD so there is no way I modified it by mistake.

Error: Physical sythesis tool PALAC is not supported by Formal Verification tool Conformal LEC.

How can I fix this?

http://www.cognitivekipple.com/store/palace.png

Thanks
B

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
	Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
	Info: Processing started: Sun Dec 21 20:13:51 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off all_01 -c all_01
Info: Found 1 design units, including 1 entities, in source file all_01.bdf
	Info: Found entity 1: all_01
Info: Found 2 design units, including 1 entities, in source file HEX2DEC.vhd
	Info: Found design unit 1: HEX2DEC-arc
	Info: Found entity 1: HEX2DEC
Info: Found 2 design units, including 1 entities, in source file CLOCK40.vhd
	Info: Found design unit 1: clock40-arc
	Info: Found entity 1: clock40
Info: Elaborating entity "all_01" for the top level hierarchy
Warning: Using design file CLOCK_SPK.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
	Info: Found design unit 1: clock_spk-arc
	Info: Found entity 1: clock_spk
Info: Elaborating entity "CLOCK_SPK" for hierarchy "CLOCK_SPK:17"
Info: Elaborating entity "clock40" for hierarchy "clock40:inst3"
Warning: Using design file CYC_PLL.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
	Info: Found entity 1: CYC_PLL
Info: Elaborating entity "CYC_PLL" for hierarchy "CYC_PLL:inst"
Info: Elaborating entity "altpll" for hierarchy "CYC_PLL:inst|altpll:altpll_component"
Info: Elaborated megafunction instantiation "CYC_PLL:inst|altpll:altpll_component"
Info: Instantiated megafunction "CYC_PLL:inst|altpll:altpll_component" with the following parameter:
	Info: Parameter "clk0_divide_by" = "5"
	Info: Parameter "clk0_duty_cycle" = "50"
	Info: Parameter "clk0_multiply_by" = "6"
	Info: Parameter "clk0_phase_shift" = "0"
	Info: Parameter "clk1_divide_by" = "1"
	Info: Parameter "clk1_duty_cycle" = "50"
	Info: Parameter "clk1_multiply_by" = "3"
	Info: Parameter "clk1_phase_shift" = "0"
	Info: Parameter "compensate_clock" = "CLK0"
	Info: Parameter "inclk0_input_frequency" = "50000"
	Info: Parameter "intended_device_family" = "Cyclone"
	Info: Parameter "lpm_type" = "altpll"
	Info: Parameter "operation_mode" = "NORMAL"
	Info: Parameter "pll_type" = "AUTO"
	Info: Parameter "width_clock" = "6"
	Info: Parameter "width_phasecounterselect" = "4"
Warning: Using design file CLOCK2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
	Info: Found design unit 1: clock2-arc
	Info: Found entity 1: clock2
Info: Elaborating entity "CLOCK2" for hierarchy "CLOCK2:inst2"
Warning: Using design file CLOCK2500.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
	Info: Found design unit 1: clock2500-arc
	Info: Found entity 1: clock2500
Info: Elaborating entity "CLOCK2500" for hierarchy "CLOCK2500:14"
Warning: Using design file clockall.gdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
	Info: Found entity 1: clockall
Info: Elaborating entity "clockall" for hierarchy "clockall:9"
Warning: Using design file CLOCK150.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
	Info: Found design unit 1: clock150-arc
	Info: Found entity 1: clock150
Info: Elaborating entity "CLOCK150" for hierarchy "clockall:9|CLOCK150:29"
Warning: Using design file CLOCK16.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
	Info: Found design unit 1: clock16-arc
	Info: Found entity 1: clock16
Info: Elaborating entity "CLOCK16" for hierarchy "clockall:9|CLOCK16:27"
Warning: Using design file DEBUGLED.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
	Info: Found design unit 1: debugled-arc
	Info: Found entity 1: debugled
Info: Elaborating entity "DEBUGLED" for hierarchy "DEBUGLED:10"
Info: Elaborating entity "HEX2DEC" for hierarchy "HEX2DEC:inst4"
Warning: Using design file HHMMSS.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
	Info: Found design unit 1: hhmmss-arc
	Info: Found entity 1: hhmmss
Info: Elaborating entity "HHMMSS" for hierarchy "HHMMSS:11"
Warning: Using design file LEDFLASH.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
	Info: Found design unit 1: ledflash-arc
	Info: Found entity 1: ledflash
Info: Elaborating entity "LEDFLASH" for hierarchy "LEDFLASH:12"
Warning: Output pins are stuck at VCC or GND
	Warning (13410): Pin "FP_DATA_DIR" is stuck at GND
	Warning (13410): Pin "SEG[8]" is stuck at GND
Warning: Output port clk0 of PLL "CYC_PLL:inst|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Warning: Design contains 5 input pin(s) that do not drive logic
	Warning (15610): No output dependent on input pin "KEY[12]"
	Warning (15610): No output dependent on input pin "KEY[11]"
	Warning (15610): No output dependent on input pin "KEY[10]"
	Warning (15610): No output dependent on input pin "KEY[9]"
	Warning (15610): No output dependent on input pin "KEY[8]"
Info: Implemented 721 device resources after synthesis - the final resource count might be different
	Info: Implemented 13 input pins
	Info: Implemented 30 output pins
	Info: Implemented 677 logic cells
	Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings
	Info: Peak virtual memory: 186 megabytes
	Info: Processing ended: Sun Dec 21 20:14:13 2008
	Info: Elapsed time: 00:00:22
	Info: Total CPU time (on all processors): 00:00:16