Use and application of a controller

[user4637]

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity controller is
port (
rst : in std_logic;
clock : in std_logic;
N : in std_logic;
Z : in std_logic;
memoryData : in std_logic_vector(7 downto 0);
DA : out std_logic;
inputSelect : out std_logic;
load : out std_logic;
memAddressSelect : out std_logic;
read : out std_logic;
FS : out std_logic_vector(3 downto 0);
PCOut : out std_logic_vector(7 downto 0);
IROut : out std_logic_vector(7 downto 0);
STOut : out std_logic_vector(3 downto 0)
);


end controller;

Architecture behavioural of controller is

type STATE is (CS_RESET, CS_FETCH, CS_DECODE, CS_LOADIM, CS_STORE, CS_LOADMEM, CS_REGOP, CS_NOOP, CS_BRAN, CS_BRAZ, CS_BRA);
signal curState: STATE := CS_RESET;
signal st_display: std_logic_vector(3 downto 0);
signal IR, PC : std_logic_vector(7 downto 0);


begin

IROut<=IR;
PCOut<=PC;

Cont: process(rst,clock)
variable opcode : std_logic_vector(2 downto 0);
begin
if(rst='0') then
curState <= CS_RESET;
PC<=(others=>'0');
IR<=(others=>'0');
opcode:=(others=>'0'); -- opcode:=IR(7 downto 5)
elsif rising_edge(clock) then
case curState is
when CS_RESET =>
PC<=(others=>'0');
IR<=(others=>'0');
opcode:=(others=>'0'); -- opcode:=IR(7 downto 5)
curState <= CS_FETCH;
when CS_FETCH =>
PC<=PC+1;
IR<=memoryData;
curState <= CS_DECODE;
when CS_DECODE =>
opcode:=IR(7 downto 5);
case opcode is
when "000" =>
curState<=CS_REGOP;
when "001" =>
curState<=CS_LOADMEM;
when "010" =>
curState<=CS_STORE;
when "011" =>
curState<=CS_LOADIM;
when "100" =>
curState<=CS_BRA;
when "101" =>
curState<=CS_BRAZ;
when "110" =>
curState<=CS_BRAN;
when "111" =>
curState<=CS_NOOP;
when others =>
curState<=CS_RESET;
end case;
when CS_REGOP =>
curState<=CS_FETCH;
when CS_LOADMEM =>
curState<=CS_FETCH;
when CS_STORE =>
curState<=CS_FETCH;
when CS_LOADIM =>
PC<=PC+1;
curState<=CS_FETCH;
when CS_BRA =>
curState<=CS_FETCH;
when CS_BRAZ =>
if(Z='1') then
PC<=memoryData;
else
PC<=PC+1;
end if;
curState<=CS_FETCH;
when CS_BRAN =>
if(N='1') then
PC<=memoryData;
else
PC<=PC+1;
end if;
curState<=CS_FETCH;
when CS_NOOP =>
PC<=PC+1;
curState<=CS_FETCH;
when others =>
curState<=CS_FETCH;
end case;
end if;
END PROCESS;

Outputs_State: process(curState)
begin
case curState is
when CS_FETCH =>
load<='0';
DA<='0';
FS<="0000";
inputSelect<='0';
memAddressSelect<='0';
read<='1';
when CS_REGOP =>
load<='0';
DA<=IR(4);
FS<=IR(3 downto 0);
inputSelect<='0';
memAddressSelect<='0';
read<='1';
when CS_LOADMEM =>
load<='1';
DA<=IR(4);
FS<="0000";
inputSelect<='1';
memAddressSelect<='1';
read<='1';
when CS_STORE =>
load<='0';
DA<='0';
FS<="0000";
inputSelect<='0';
memAddressSelect<='1';
read<='0';
when CS_LOADIM =>
load<='1';
DA<=IR(4);
read<='1';
inputSelect<='1';
memAddressSelect<='0';
FS<="0000";
when CS_BRA =>
load<='0';
DA<='0';
FS<="0000";
inputSelect<='0';
memAddressSelect<='0';
read<='1';
when CS_BRAZ =>
load<='0';
DA<='0';
FS<=IR(3 downto 0);
inputSelect<='0';
memAddressSelect<='0';
read<='1';
when CS_BRAN =>
load<='0';
DA<='0';
FS<=IR(3 downto 0);
inputSelect<='0';
memAddressSelect<='0';
read<='1';
when CS_NOOP =>
load<='0';
DA<='0';
FS<="0000";
inputSelect<='0';
memAddressSelect<='0';
read<='1';
when others =>
load<='0';
DA<='0';
FS<="0000";
inputSelect<='0';
memAddressSelect<='0';
read<='1';
end case;
END PROCESS;

STOut <= "1111" when (curState = CS_RESET) else
"1100" when (curState = CS_FETCH) else
"1000" when (curState = CS_DECODE) else
"0000" when (curState = CS_REGOP) else
"0001" when (curState = CS_LOADMEM) else
"0010" when (curState = CS_STORE) else
"0011" when (curState = CS_LOADIM) else
"0100" when (curState = CS_BRA) else
"0101" when (curState = CS_BRAZ) else
"0110" when (curState = CS_BRAN) else
"0111" when (curState = CS_NOOP) else
"1110" ;


end architecture behavioural;