URGENT HELP!!! for an error message

[bandgap]

hi
im using model sim to compile some of my vhdl codes. but, i see an error message, which i couldnt be able to solve up to now, while compiling one of my .vhd file.
the error message is:

# ** Error: F:/Master Courses/EE 598/EA HW2/ALU16BIT_ENTITY.vhd(22): Cannot resolve slice name as type std.standard.bit.
# ** Error: F:/Master Courses/EE 598/EA HW2/ALU16BIT_ENTITY.vhd(22): Cannot resolve slice name as type std.standard.bit.
# ** Error: F:/Master Courses/EE 598/EA HW2/ALU16BIT_ENTITY.vhd(30): Cannot resolve slice name as type std.standard.bit.
# ** Error: F:/Master Courses/EE 598/EA HW2/ALU16BIT_ENTITY.vhd(30): Cannot resolve slice name as type std.standard.bit.
# ** Error: F:/Master Courses/EE 598/EA HW2/ALU16BIT_ENTITY.vhd(35): VHDL Compiler exiting

this error message is for the BOLD LINES in the code.
the code:

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.BASIC_BLOCKS.ALL;
USE WORK.COMPLEX_BLOCKS.ALL;
USE WORK.BASIC_GATES.ALL;

ENTITY alu16bit IS
GENERIC(one_delay: TIME := 2 NS);
PORT(IN1, IN2: IN BIT_VECTOR(15 DOWNTO 0); SEL: IN BIT_VECTOR(3 DOWNTO 0);
S: OUT BIT_VECTOR(15 DOWNTO 0));
END alu16bit;

ARCHITECTURE structure OF alu16bit IS
SIGNAL IN1_int, IN2_int, C_int, S_int, Cout_int, Stemp_int, IN2bar_int: BIT_VECTOR(15 DOWNTO 0);
SIGNAL wire: BIT_VECTOR(3 DOWNTO 0);
BEGIN
IN1_int <= IN1;
IN2_int <= NOT IN2;

mux00: mux2to1 GENERIC MAP(one_delay) PORT MAP(IN2(0), IN2_int(0), SEL(3), IN2_int(0));
wire(3 DOWNTO 0) <= ('0'&'1'&SEL(3)&'0');
mux1: mux4bit GENERIC MAP(one_delay) PORT MAP(wire(3 DOWNTO 0), SEL(2 DOWNTO 1), C_int(0));
mux2: mux2to1 GENERIC MAP(one_delay) PORT MAP(S_int(0), Cout_int(0), SEL(0), Stemp_int(0));
fa0: FA GENERIC MAP(one_delay) PORT MAP(IN1_int(0), IN2_int(0), C_int(0), S_int(0), Cout_int(0));

fai: FOR i IN 15 DOWNTO 1
GENERATE
mux0i: mux2to1 GENERIC MAP(one_delay) PORT MAP(IN2(i), IN2_int(i), SEL(3), IN2_int(i));
wire((i+1)*4-1 DOWNTO i*4) <= ('0'&'1'&Cout_int(i-1)&'0');
mux1i: mux4bit GENERIC MAP(one_delay) PORT MAP(wire((i+1)*4-1 DOWNTO i*4), SEL(2 DOWNTO 1), C_int(i));
mux2i: mux2to1 GENERIC MAP(one_delay) PORT MAP(S_int(i), Cout_int(i), SEL(0), Stemp_int(i));
fa1: FA GENERIC MAP(one_delay) PORT MAP(IN1_int(i), IN2_int(i), C_int(i), S_int(i), Cout_int(i));
END GENERATE;
S <= Stemp_int;
END structure;

 

[blacktom]

Hello Bandgap,

One question, how does the port map of the component mux4bit looks like?

 

[bandgap]

here is the full code for mux4bit blacktom

ENTITY mux4bit IS
GENERIC(one_delay : TIME := 2 NS);
PORT(IN1: IN BIT_VECTOR(3 DOWNTO 0); SEL: IN BIT_VECTOR(1 DOWNTO 0); OUT1: OUT BIT);
END mux4bit;

ARCHITECTURE structure OF mux4bit IS
SIGNAL internal_IN1: BIT_VECTOR(3 DOWNTO 0);
SIGNAL internal_SEL: BIT_VECTOR(1 DOWNTO 0);
BEGIN
internal_SEL <= NOT SEL;
g1: nand3 GENERIC MAP(3*one_delay) PORT MAP(IN1(0), internal_SEL(1), internal_SEL(0), internal_IN1(0));
g2: nand3 GENERIC MAP(3*one_delay) PORT MAP(IN1(1), internal_SEL(1), SEL(0), internal_IN1(1));
g3: nand3 GENERIC MAP(3*one_delay) PORT MAP(IN1(2), SEL(1), internal_SEL(0), internal_IN1(2));
g4: nand3 GENERIC MAP(3*one_delay) PORT MAP(IN1(3), SEL(1), SEL(0), internal_IN1(3));
g5: nand4 GENERIC MAP(4*one_delay) PORT MAP(internal_IN1(3), internal_IN1(2), internal_IN1(1), internal_IN1(0),OUT1);
END structure;

 

[blacktom]

Hello Bandgap,

I think i found something what the problem is.

The fault is in the following piece of the code

SIGNAL wire: BIT_VECTOR(3 DOWNTO 0);

fai: FOR i IN 15 DOWNTO 1
GENERATE
mux0i: mux2to1 GENERIC MAP(one_delay) PORT MAP(IN2(i), IN2_int(i), SEL(3), IN2_int(i));
wire((i+1)*4-1 DOWNTO i*4) <= ('0'&'1'&Cout_int(i-1)&'0');

The signal wire is only declared for (3 downto 0) but in
this loop it is declared for example when i=15 (for 63 downto 60). It is in the same scope (4 bits) but out of range of the wire declaration.

I think you have to find another way to wire your conenctions.

hope it helps

Blacktom

 

[bandgap]

thanx for the idea blacktom. i will try it..
best regards...