hi all,
its my first post on this forum so if this is posted in the wrong section plz let me know. Now to ask my question.
I created this piece of code that is supposed to be a digital dice. I can make it work with 1 7-seg but not with 2.
I think i have found the correct way to program it, when i try and build he dousnt add 2 inputs(S1 and S2). I get a warning that they are unused. I'll post the code below so u guys could help me out a bit.
its my first post on this forum so if this is posted in the wrong section plz let me know. Now to ask my question.
I created this piece of code that is supposed to be a digital dice. I can make it work with 1 7-seg but not with 2.
I think i have found the correct way to program it, when i try and build he dousnt add 2 inputs(S1 and S2). I get a warning that they are unused. I'll post the code below so u guys could help me out a bit.
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dobbelsteen is
port( clock : in std_logic;
S1 : in std_logic;
S2 : in std_logic;
aan : in std_logic;
enable: out std_logic_vector(3 downto 0);
leds : out std_logic_vector(1 to 7)
);
end dobbelsteen;
architecture Behavioral of dobbelsteen is
signal teller : std_logic_vector(3 downto 0):="0001";
signal clk : std_logic;
signal dummy : std_logic_vector(22 downto 0);
signal aan2 : std_logic;
begin
process(clk)
begin
if clock'event and clock ='1' then
dummy <= dummy+1;
end if;
end process;
clk <= dummy(22);
process (clk)
begin
if clk'event and clk = '1' then
if aan = '1' and aan2 = '1' then
teller <= teller+1; -- zorgt ervoor dat er een 0 staat wanneer
if teller > "0110" then -- de dobbelsteen aan het draaien is.
teller <= "0001";
end if;
end if;
if S1 = '1' then
aan2 <= '1';
enable(0) <= '0';
enable(1) <= '1';
enable(2) <= '1';
enable(3) <= '1';
if S1 = '0' then
aan2 <= '0';
if S2 = '1' then
aan2 <= '1';
enable(0) <= '1';
enable(1) <= '0';
enable(2) <= '1';
enable(3) <= '1';
if S2 = '0' then
aan2 <= '0';
end if;
end if;
end if;
end if ;
end if;
end process;
process (teller)
begin
case teller is -- abcdefg
WHEN "0001" => leds <= "1001111"; --"0110000"
WHEN "0010" => leds <= "0010010"; --"1101101"
WHEN "0011" => leds <= "0000110"; --"1111001"
WHEN "0100" => leds <= "1001100"; --"0110011"
WHEN "0101" => leds <= "0100100"; --"1011011"
WHEN "0110" => leds <= "0100000"; --"1011111"
WHEN OTHERs => leds <= "1111111"; --"0000000"
end case;
end process;
end Behavioral;