Unable to initialize RAM module

[ctunder77]

Hi,
I am using Xilinx's ISE Webpack software to make a FIR filter. I have already designed the memory control module and the ROM module to store my coefficients. I was able to initialise the ROM using a series of signal statements. However, my filter design uses a RAM to store the incoming samples and to test my memory control module i would like to initialize the RAM with some known values.
At first i tried this using the same series of signal assignments i used with the ROM. This was to no avail as when i simulate the RAM's testbench in modelsim it tells me the values within the RAM are uninitialized. (UUUUUUUU). I do not know why the signal assignment method did not work since it worked with the ROM.
I also tried the write values to the ROM and verify that they were written using the waveforms in the testbench but that method gives me the same unitialized array as before.
Can someone help me please? Below is my code for the ROM and then for the RAM.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rom is
port (
MASTER_CLOCK : in std_logic;
ROM_ADRESS_IN : in std_logic_vector(6 downto 0);
COEFFICIENT_OUT : out std_logic_vector(15 downto 0));
end rom;

architecture syn3 of rom is

type rom_type is array (63 downto 0) of std_logic_vector (15 downto 0);
signal ROM : rom_type;
signal read_add : std_logic_vector(6 downto 0);

begin

ROM(0) <= &quot;0000000000000001&quot;;
ROM(1) <= &quot;0000000000000010&quot;;
ROM(2) <= &quot;0000000000000011&quot;;
ROM(3) <= &quot;0000000000000100&quot;;
ROM(4) <= &quot;0000000000000101&quot;;
ROM(5) <= &quot;0000000000000110&quot;;
ROM(6) <= &quot;0000000000000111&quot;;
ROM(7) <= &quot;0000000000001000&quot;;
ROM(8) <= &quot;0000000000001001&quot;;
ROM(9) <= &quot;0000000000001010&quot;;
ROM(10) <= &quot;0000000000001011&quot;;
ROM(11) <= &quot;0000000000001100&quot;;
ROM(12) <= &quot;0000000000001101&quot;;
ROM(13) <= &quot;0000000000001110&quot;;
ROM(14) <= &quot;0000000000001111&quot;;
--ROM(15) <= &quot;0000000000001111&quot;;
ROM(15) <= &quot;0000000000010000&quot;;
ROM(16) <= &quot;0000000000010001&quot;;
ROM(17) <= &quot;0000000000010010&quot;;
ROM(18) <= &quot;0000000000010011&quot;;
ROM(19) <= &quot;0000000000010100&quot;;
ROM(20) <= &quot;0000000000010101&quot;;
ROM(21) <= &quot;0000000000010110&quot;;
ROM(22) <= &quot;0000000000010111&quot;;
ROM(23) <= &quot;0000000000011000&quot;;
ROM(24) <= &quot;0000000000011001&quot;;
ROM(25) <= &quot;0000000000011010&quot;;
ROM(26) <= &quot;0000000000011011&quot;;
ROM(27) <= &quot;0000000000011100&quot;;
ROM(28) <= &quot;0000000000011101&quot;;
ROM(29) <= &quot;0000000000011110&quot;;
ROM(30) <= &quot;0000000000011111&quot;;
ROM(31) <= &quot;0000000000100000&quot;;
ROM(32) <= &quot;0000000000100001&quot;;
ROM(33) <= &quot;0000000000100010&quot;;
ROM(34) <= &quot;0000000000100011&quot;;
ROM(35) <= &quot;0000000000100100&quot;;
ROM(36) <= &quot;0000000000100101&quot;;
ROM(37) <= &quot;0000000000100110&quot;;
ROM(38) <= &quot;0000000000100111&quot;;
ROM(39) <= &quot;0000000000101000&quot;;
ROM(40) <= &quot;0000000000101001&quot;;
ROM(41) <= &quot;0000000000101010&quot;;
ROM(42) <= &quot;0000000000101011&quot;;
ROM(43) <= &quot;0000000000101100&quot;;
ROM(44) <= &quot;0000000000101101&quot;;
ROM(45) <= &quot;0000000000101110&quot;;
ROM(46) <= &quot;0000000000101111&quot;;
ROM(47) <= &quot;0000000000110000&quot;;
ROM(48) <= &quot;0000000000110001&quot;;
ROM(49) <= &quot;0000000000110010&quot;;
ROM(50) <= &quot;0000000000110011&quot;;
ROM(51) <= &quot;0000000000110100&quot;;
ROM(52) <= &quot;0000000000110101&quot;;
ROM(53) <= &quot;0000000000110110&quot;;
ROM(54) <= &quot;0000000000110111&quot;;
ROM(55) <= &quot;0000000000111000&quot;;
ROM(56) <= &quot;0000000000111001&quot;;
ROM(57) <= &quot;0000000000111010&quot;;
ROM(58) <= &quot;0000000000111011&quot;;
ROM(59) <= &quot;0000000000111100&quot;;
ROM(60) <= &quot;0000000000111101&quot;;
ROM(61) <= &quot;0000000000111110&quot;;
ROM(62) <= &quot;0000000000111111&quot;;
ROM(63) <= &quot;0000000001000000&quot;;

process (MASTER_CLOCK)
begin
if( MASTER_CLOCK'event and MASTER_CLOCK = '1' ) then
read_add <= ROM_ADRESS_IN;
COEFFICIENT_OUT <= ROM(conv_integer(ROM_ADRESS_IN));
end if;
end process;

end syn3;

-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity ram1 is
port (MASTER_CLOCK : in std_logic;
WRITE_EN_1 : in std_logic;
RAM_1_ADRESS : in std_logic_vector(5 downto 0);
SAMPLE_IN_1 : in std_logic_vector(7 downto 0);
SAMPLE_OUT_1 : out std_logic_vector(7 downto 0));
end ram1;

architecture syn of ram1 is

type ram_1_type is array (31 downto 0) of std_logic_vector (7 downto 0);
signal RAM : ram_1_type;
signal read_add : std_logic_vector(5 downto 0);

begin

RAM(0) <= &quot;00000001&quot;;
RAM(1) <= &quot;00000010&quot;;
RAM(2) <= &quot;00000011&quot;;
RAM(3) <= &quot;00000100&quot;;
RAM(4) <= &quot;00000101&quot;;
RAM(5) <= &quot;00000110&quot;;
RAM(6) <= &quot;00000111&quot;;
RAM(7) <= &quot;00001000&quot;;
RAM(8) <= &quot;00001001&quot;;
RAM(9) <= &quot;00001010&quot;;
RAM(10) <= &quot;00001011&quot;;
RAM(11) <= &quot;00001100&quot;;
RAM(12) <= &quot;00001101&quot;;
RAM(13) <= &quot;00001110&quot;;
RAM(14) <= &quot;00001111&quot;;
RAM(15) <= &quot;00010000&quot;;
RAM(16) <= &quot;00010001&quot;;
RAM(17) <= &quot;00010010&quot;;
RAM(18) <= &quot;00010011&quot;;
RAM(19) <= &quot;00010100&quot;;
RAM(20) <= &quot;00010101&quot;;
RAM(21) <= &quot;00010110&quot;;
RAM(22) <= &quot;00010111&quot;;
RAM(23) <= &quot;00011000&quot;;
RAM(24) <= &quot;00011001&quot;;
RAM(25) <= &quot;00011010&quot;;
RAM(26) <= &quot;00011011&quot;;
RAM(27) <= &quot;00011100&quot;;
RAM(28) <= &quot;00011101&quot;;
RAM(29) <= &quot;00011110&quot;;
RAM(30) <= &quot;00011111&quot;;
RAM(31) <= &quot;00100000&quot;;


process (MASTER_CLOCK)
begin
if( MASTER_CLOCK'event and MASTER_CLOCK = '1') then
if (WRITE_EN_1 = '1') then
RAM(conv_integer(RAM_1_ADRESS)) <= SAMPLE_IN_1;
end if;
read_add <= RAM_1_ADRESS;

SAMPLE_OUT_1 <= RAM(conv_integer(RAM_1_ADRESS));
end if;
end process;

end syn;

 

[senjed]

A signal cam't be assigned in two processes. that's one basic rule in VHDL. This means that the way you acted for initialization, not only doesn't do your job, but denies the RAM from working properly. you'll never be able to put something in it, and you'll get X whenever you try to.
In fact the only way for initialization of a sequential circuit is to use a RESET. Oc coourse there are some sort of initialization without explicit reset in Xilinx FPGAs (when the FPGA is powering up), especially for RAM blocks, but I'm not so familiar with the details.

By the way, how a RAM is this? You always read the thing you're just writing on? shouldn't read and write addresses be seperate?

 

[ctunder77]

Thank you for your reply Senjed,

I am currently away from my work station but was just wondering if you could expand on why one is unable to assign signal in two processes. I am a beginner to VHDL and do not own a book on the subject either so I am not familiar with some of the basic tenants of VHDL.
If I cannot assign signals to initialise my ROM in one process and assign signals to initialise my RAM in another process how can I initialise them both seeing as they are separate entities?
On your question of why are the read and write adresses the same on the RAM. The algorithm of the FIR filter I'm implementing would not seem to benefit greatly from it especially with the memory control structure I am using.(At least in my opinion)
Once again thank you for your help Senjed.

Ctunder

 

[naraic]

Correct me if I am wrong.

I believe that you can assign std_logic signals in different processes. However, for example, if one process assigns a '1', and the other assigns a '0' at the same time, the result will be 'X'.

There is a table somewhere that goes through all the results from the possible inputs (e.g. '0', '1', 'X', 'U', '-', etc.).

Other signal types (e.g. std_ulogic) will generally give an error at compile time.

Ciaran

 

[naraic]

By the way, it is usually considered bad design practice, to assign the same signal in two different processes, even if it does not give an error