unable to generate a pulse on external pin event 1

[aixil]

Hello,
I want to generate a pulse when the state of the pin FCTRL_VLD_L of my virtex xcv1000 FPGA changes from high to low.

I tried:

pulse : process
begin
wait until fctrl_vld_l'event and fctrl_vld_l='0';
pulsesignal <= '1', '0' after 100 ns;
end process;

This code synthetize, but when i load the desing on the FPGA, the signal pulsesignal remains '1' after the event.

Can anyone tell me how to generate this pulse signal?

regards,

alexis

 

[RVSachin]

The issues with your designs are:
1. When you mention the following line
fctrl_vld_l'event and fctrl_vld_l='0'
fctrl_vld_l will be treated as a clock signal. Are you sure that this is a periodic clock signal?

2. Since you are assigning '1' to pulsesignal under this clock edge, this assignment infers a flip-flop and therefore will retain a value of '1' always, irrespective of the usage of the 'AFTER' clause.

This is because, the after clause has no meaning in synthesis and it is ignored by the synthesis tools. There's no hardware for AFTER clause. It's only a term meant for simulation.

If the fctrl_vld_l is periodic or if it goes low under a clock edge, then you can generate the pulse, but again, the pulse width should be known (may be equivalent to clock period).

 

[aixil]

Thanks for your answer.

1. fctrl_vld_l is NOT a periodic clock signal. It is an input pin of the FPGA that goes low only once. It does not necessary go low under a clock edge. (it is a pin used for host-fpga communications).

2. I have another periodic clock signal in my design. How can i generate a pulse (of width 1 clock cycle for example) when the fctrl_vld_l input goes low?

 

[bfuchs]

You MUST have a periodic clock signal in order to check the external pin. It should also be a reasonable frequency. You are essentally sampling the input pin, and need to be able to detect a change on the external pin. If the clock were really slow (say 1 Hz) you could easily miss a button being pressed. If it is a higher frequency (say 100 KHz), you would be checking the line 100,000 times per second.

Now, what is driving the fctrl_vld_l pin? If it is a button, you need to either debounce the button outside the FPGA, or provide a decent edge-detection routine in VHDL.

If the signal is debounced or from another logic chip, all you need to do is double-register the signal to synchronize it to your clock:

signal input_pin : std_logic_vector(1 downto 0);
signal RisingEdge : std_logic; -- will pulse on hi edge
signal FallingEdge: std_logic; -- will pulse on low edge

process(clk) -- Assumes fctrl_vld_l is DEBOUNCED!
begin
if rising_edge(clk) then
input_pin <= input_pin(0) & fctrl_vld_l;
case input_pin(1 downto 0) is
when &quot;01&quot; => RisingEdge <= '1';
FallingEdge <= '0';
when &quot;10&quot; => RisingEdge <= '0';
FallingEdge <= '1';
when others => RisingEdge <= '0';
FallingEdge <= '0';
end case;
end if;
end if;

The signal input_pin is a vector (twoflops) which we will use as a shift register. This sounds really complicated, but we are just using it to keep track of fctrd_vld_l for two consecutive clocks.

input_pin(1) represetns the state of fctrd_vld_l two clocks ago.
input_pin(0) represetns the state of fctrd_vld_l one clock ago.

input_pin <= input_pin(0) & fctrl_vld_l is a short-hand way of saying:
input_pin(1) <= input_pin(0);
input_pin(0) <= fctrl_vld_l;

The 'case' statement is used to examine the values of input_pin to see if we detect a rising or falling edge.

Think about it: if we know the value of fctrl_vld_l during any two consecutive clocks, we will be able to see an edge.

Assume that fctrl_vld_l changes from low to high to low over a period of time.

Using our clock to sample the line, our flops may look like:

fctrl_vld_l: 0110000
input_pin(0): 0011000
input_pin(1): 0001100

Any given column represents the flops sampled at a rising clock edge.

In our case statement we look at input_pin(1 downto 0):
input_pin(0): 0001100
input_pin(1): 0000110

input_pin(1 downto 0)= &quot;01&quot; represents a rising edge of fctrl_vld_l.
&quot;10&quot; represents a falling edge.
&quot;11&quot; means fctrl_vld_l has been high for at least two clocks.
&quot;00&quot; means fctrl_vld_l has been low for at least two clocks.

We set FallingEdge or FallingEdge at &quot;10&quot; or &quot;01&quot;, respectively. We clear them when we don't see that condition any more. This gaurantees a single-clock pulse on a rising or falling edge.

NOTE: A beginner way of writing this process is:

signal input_pin1 : std_logic;
signal input_pin0 : std_logic;
signal RisingEdge : std_logic; -- will pulse on hi edge
signal FallingEdge: std_logic; -- will pulse on low edge
process(clk) -- Assumes fctrl_vld_l is DEBOUNCED!
begin
if rising_edge(clk) then
input_pin0 <= fctrl_vld_l;
input_pin1 <= input_pin0;
if input_pin1='1' and input_pin0='0' then
RisingEdge <= '1';
Falling_Edge <= '0';
elsif input_pin1='0' and input_pin0='1' then
RisingEdge <= '0';
Falling_Edge <= '1';
else
RisingEdge <= '0';
Falling_Edge <= '0';
end if;
end if;
end process;

Do yourself a favor, and try to understand the first method. If you do, you will have a head start on the rest of the class!

Good Luck!