Trying to synthesise FSM

[cdchilds]

Hi,

I am currently developing an 8-channel event logger in VHDL to replace an existing 8051 assembly routine that is too slow. When completed, the PLD will interface with the 8051, which will pass commands over a bus and expect the logger to respond with the timer values that it has logged for the 8 channels.

As this is my first VHDL undertaking, I have had some trouble writing the code, as I'm sure you will appreciate However, I am now happy with my behavioural simulations and would like to progress to synthesising the design.

The implementation is based upon 3 entities;
- A "Controller" that communicates with the 8051 over an external bus, and controls each of the Sensor handlers
- Eight "Sensor handlers" that are each responsible for logging events on one of the sensor inputs
- A 16-bit counter that is instantiated in the Controller and each of the 8 sensor handlers (all fed with the same clock to avoid distributing the 16-bit counter value to all entities)
I have built the top-level design using direct connections between the controller, sensor handlers and external connections (i.e. drawn a schematic).

The Controller has turned out to be a fairly large state machine, as it must handle various commands and communicate over 2 buses (external bus to communicate with 8051, and internal bus to communicate with the 8 sensor handlers). It has 31 states. The Sensor handler entity is also an FSM, but this has only 7 states.

When I try to synthesise the top-level design with XST, I get HDL Analysis errors, presumably because I have violated some (if not all of the 'unwritten rules' of writing synthesisable VHDL. I don't fully understand what the rules are, so I'm having difficulty rewriting the code to make it synthesisable.

Is it strictly necessary to assign a value to every output in each possible execution path of the process? To do this I would have to increase the number of states considerably, as some of the states do not know the correct value for some of the outputs, as they depend on the previous path through the state machine.

FYI, I am using Xilinx ISE Webpack 6 for development, with Modelsim XE II 5.7c for simulation.

Any guidance at all would be greatly appreciated.

Thanks,

Chris.

PS Here are the error messages from XST; I hope that they help to indicate where I might be going wrong.

-------------------

=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file C:/Xilinx/bin/testproject/counter16.vhd in Library work.
Architecture behavioral of Entity counter16 is up to date.
Compiling vhdl file C:/Xilinx/bin/testproject/controller.vhd in Library work.
Architecture combination of Entity controller is up to date.
Compiling vhdl file C:/Xilinx/bin/testproject/sensorhandler.vhd in Library work.
Architecture combination of Entity sensorhandler is up to date.
Compiling vhdl file C:/Xilinx/bin/testproject/logger8sh.vhf in Library work.
Architecture behavioral of Entity logger8sh is up to date.

=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <logger8sh> (Architecture <behavioral>).
Entity <logger8sh> analyzed. Unit <logger8sh> generated.

Analyzing Entity <controller> (Architecture <combination>).
INFO:Xst:1304 - Contents of register <internalBus> in unit <controller> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <hold> in unit <controller> never changes during circuit operation. The register is replaced by logic.
ERROR:Xst:677 - C:/Xilinx/bin/testproject/controller.vhd line 330: Illegal constants on arithmetic operators.
-->

Total memory usage is 59328 kilobytes

-------------------

 

[berett]

The code would be much more helpful here. There are ca 2.5 different ways of writing the reasonable FSM. Your decision - probably someone here could improve the code, just for fun.

Anyway according to

&quot;...Is it strictly necessary to assign a value to every output in each possible execution path of the process? ...&quot;

It is not, but it is very recommended from hardware point of view. If you do not precise what happens to the particular output under some condition it is assumed that you want it to keep the last value (something must be done to the poor signal, yo?). The only hardware to do that is a latch. If this is asynchronous latch you violate the DFT rules. Eventually the asynchronous latches are not welcome in any designs although in the FPGA context.

What you can do is

Process

begin

troublesomeoutput_1 <= '0' -- e.g.
troublesomeoutput_2 <= something equally stupid -- etc

then your original FSM code with case, if etc.

end process

What you need is the set of safe values you can force the outputs to be if they're &quot;not necessary&quot; or &quot;not needed&quot;
in the given condition branch ...

This way you convert the latches to muxes without much coding effort.

have fun
or send the code, who knows ...

rgds
berett