tri-state buses 1

[yourangel]

Need help!
I'm trying to implement a tdm system based on a cpld, the trouble here is that I need to use a tri-state bus, so, how can I use it? how is it declared? need practical examples 'cause I've found syntax examples only.
Another cuestion, how can I repair a "process clocking is too complex" error?
tnx!

 

[jeandelfrigo]

Yourangel,

Most modern CPLD have tri state IO capability these days, however it might be wise to check if the CPLD you use supports this or not and if there are limitations (number of IOs, etc).

Describing a tri state buffer in VHLD is not that difficult.

output is output port on the entity.
DataOut is internal signal of same size
OE is the output enable signal that is active high when you want the bus to drive.

output <= DataOut when OE = '1' else 'Z'; --(when std_logic)

output <= DataOut when OE = '1' else (others => 'Z'); --(when std_logic_vector)

Another way is instantiating a primitive. This is a dedicated peace of hardware in the device.

For example for a Xilinx device :

i_OBUFT : OBUFT
port map (
I => DataOut,
O => output,
T => OE
);

You can find these primitives in the design tool documentation under the libraries section. Mostly a list of devices that support this primitive is included.

The same is true for other PLD manufacturers.

I hope this helps, if you need more info just say so.

regards

jeandelfrigo