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Transmission Gates ??
- Thread starter aryajur
- Start date
Wow ... just for fun ?
First - transmission gate is something that does not reveal a purely digital nature. Thus there is no possibility to create a synthesizable code for it. (I.e providing creating appropriate hardware). Excluding just instantiating a component from the library - if you can find one ...
But it is possible to create a model using e.g. digital constructs for the input and appropriate kind of output - maybe the REAL numbers representing the resistance, maybe the enumeration type for OPEN/CLOSE action or maybe just digital '0' '1' (or 'Z' - consider this!) representing some features you are interested in. Depends on how you perceive the functionality - or which part of it you are interested in. So using the if-else constructs together with the appropriate data types, you can play with it and you can even try to connect it with serious digital hardware (I mean the signals of the reasonable type) !!!
That's something like simulating the A/D converter the input is REAL number, the output is std_logic_vector, then some formulas an muxes inside, add transport or inertial delay, then connect to the serious logic (why not) and ... have fun !!!
rgds
P.S. maybe VHDL-AMS would provide more possibilities
(I mean more fun, for the moment ...)
First - transmission gate is something that does not reveal a purely digital nature. Thus there is no possibility to create a synthesizable code for it. (I.e providing creating appropriate hardware). Excluding just instantiating a component from the library - if you can find one ...
But it is possible to create a model using e.g. digital constructs for the input and appropriate kind of output - maybe the REAL numbers representing the resistance, maybe the enumeration type for OPEN/CLOSE action or maybe just digital '0' '1' (or 'Z' - consider this!) representing some features you are interested in. Depends on how you perceive the functionality - or which part of it you are interested in. So using the if-else constructs together with the appropriate data types, you can play with it and you can even try to connect it with serious digital hardware (I mean the signals of the reasonable type) !!!
That's something like simulating the A/D converter the input is REAL number, the output is std_logic_vector, then some formulas an muxes inside, add transport or inertial delay, then connect to the serious logic (why not) and ... have fun !!!
rgds
P.S. maybe VHDL-AMS would provide more possibilities
(I mean more fun, for the moment ...)
heh heh,
My responce was the same as berett. First I had to look up what a transmission gate was because its been a while since school (which was the last time I ever had to look at one of these things).
Then I laughed and said ouch. But it could be done for a behavioural model. Not too difficult, just some hard thinking to make sure you cover all the possiblities.
My responce was the same as berett. First I had to look up what a transmission gate was because its been a while since school (which was the last time I ever had to look at one of these things).
Then I laughed and said ouch. But it could be done for a behavioural model. Not too difficult, just some hard thinking to make sure you cover all the possiblities.
- Thread starter
- #4
Thank you guys for the help.
Well I had asked the question because I wanted to model an edge triggered (Master slave ) D flip flop. This flip flop is realised using only 4 transmission gates and 5 inverters. So if now in VHDL I cannot make a structural model of a transmission gate how will this type of flip flop be synthesized?
Well I had asked the question because I wanted to model an edge triggered (Master slave ) D flip flop. This flip flop is realised using only 4 transmission gates and 5 inverters. So if now in VHDL I cannot make a structural model of a transmission gate how will this type of flip flop be synthesized?
If I uderstand it well ....
you shall just write "something stupid like ..."
process(clk,reset)
begin
if reset = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
this is the behavioural description of the rising edge of clk triggered D flip fliop. With asynchronous reset.
However it is recognised (and preferred) by all the synthesis tools which seeing the magic line
elsif clk'event and clk = '1' then
invoke from the library the clk triggered D flip-flop for any signal "on the left" (like q<= )until the
end if;
line comes.
Same about simulation tools.
(if I understood your need well ...)
rgds
you shall just write "something stupid like ..."
process(clk,reset)
begin
if reset = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
this is the behavioural description of the rising edge of clk triggered D flip fliop. With asynchronous reset.
However it is recognised (and preferred) by all the synthesis tools which seeing the magic line
elsif clk'event and clk = '1' then
invoke from the library the clk triggered D flip-flop for any signal "on the left" (like q<= )until the
end if;
line comes.
Same about simulation tools.
(if I understood your need well ...)
rgds
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