timing constraints

[naraic]

Hi,

I am doing a project that uses a 100MHz clock. Within the project I use two DCMs, one to double the clock to 200MHz, and another to double and phase shift the clock.

When I run XST on the project, It tells me that the max frequency is ~105MHz, which is good for me, as it is over 100MHz.

However when I place&route I get errors with the timing constraints not being met (I have a constraints file with timing constraints of 10ns period and 50% high time). Apparently, the minimum period is about ~15ns. Also, one of the DCM clocks violate their constraints (but not both DCMs).

Is their any setting I could change or something?

Thanks
Ciarán

 

[VHDLguy]

You say that you are doubling the clock frequency to 200 Mhz, but XST gives you a max frequency of 105 Mhz.

I would assume that most of your logic is running at this double frequency of 200Mhz. I don't use XST but it would make sense that the reported max frequency is the slowest path (between two flip-flops) that it can find in the design. Given that you are likely(?) running at 200Mhz between those two flip-flops then you should actually be aiming for a max frequency of 200Mhz, not your input clock of 100Mhz.

There maybe some settings to help, but it probably won't help that much (another 95 Mhz).

You may need to rethink your coding.

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http://www.lateralsands.com/

 

[naraic]

XST (in Xilinx ISE) tracks all the clock frequencies. Some of my core uses 100MHz, some uses 200MHz. The timing constraints reported are for the top level (i.e. the input clock). Therefore the max frequency for the input is 105MHz, and theoretically, 210MHz for the doubled clock.

But I don't think this is where the problem lies. I know that the report given in synthesis is not fully accurate, and that the place and route is more accurate. But surely the difference shouldn't be 50%?

Thanks
Ciarán

 

[VHDLguy]

hmm Interesting way of doing things.

All the synthesizers/fitters/etc I have used have always shown worst case paths for every clock domain. And when you add a DCM or anything that would change the clock it simply creates a new clock domain and reports for that new domain. I will be starting to use XST in the next few months, but can't help you right now.

Ignoring that, you are right, 50% is pretty large. Is your device very full? or do you have lots of extra space left?

I assume this is an interal path and not a path going to an IO pad?

have you looked at the path to see if it goes all over the FPGA? Maybe it will be more obvious what is the problem with an eyeball at it.

Are you floor planning at a block level or just letting the tool put things where it pleases? I have seen people trying to floorplan blocks all over the device, but then having a signal that goes through lots of blocks without any flip-flops... naturally if the tool try's to keep to the floorplanning it ends up creating huge amounts of routing. (although I've never seen this in FPGAs, most tools seem to just ignore the floorplanning and move the logic it needs to move).

oh, i forgot - are there lots of paths out of timing, or just a few?


--

http://www.lateralsands.com/