bartdiricx
Programmer
Hello,
We're using TCL as our build script for our FPGA (= programmable HW) builds. This is done on top of xtclsh, a Xilinx (= FPGA vendor) specific command layer with support for TCL.
The problem is that an FPGA build can sometimes take several hours. An FPGA build has several steps, one of them is invoking the placer (to place the logic in the device) and router (to route the connections between the placed logic). This is done by executing the following call: process run "Place & Route"
Now this call is blocking, it only returns when the placer and router have finished (or failed). Normally this takes about 1 or 2 hours, but occasionally it takes over 20 hours. In this case I want to stop the placer and router, make some option changes and retry.
So how can I make sure that this call (process run "Place & Route") is interrupted after a given timeout?
Best regards,
Bart
We're using TCL as our build script for our FPGA (= programmable HW) builds. This is done on top of xtclsh, a Xilinx (= FPGA vendor) specific command layer with support for TCL.
The problem is that an FPGA build can sometimes take several hours. An FPGA build has several steps, one of them is invoking the placer (to place the logic in the device) and router (to route the connections between the placed logic). This is done by executing the following call: process run "Place & Route"
Now this call is blocking, it only returns when the placer and router have finished (or failed). Normally this takes about 1 or 2 hours, but occasionally it takes over 20 hours. In this case I want to stop the placer and router, make some option changes and retry.
So how can I make sure that this call (process run "Place & Route") is interrupted after a given timeout?
Best regards,
Bart