test bench problem

[Guest_imported]

Hi, i'm new in VHDL and have a little problem, i can't simulate the entity i just created.
The 'thing' is a palindrome word detector, it has 4 inputs (clock, reset, data, sync) and 1 output (z=1 if palindrome, z=0 if not).
The first 5 bits in the data line are the length of the word to be detected. (so, data= length+word).
To synchronize the 'thing' the sync line goes high for a while when new data arrives.
Well after this short introduction, the problem is that i have made all the proggie and when i try to test'it. (guss... yeah.. doesn't work). The data is take from a txt file and the output is also writen to one.
Following i paste the code of the test bench, PLEEEEEEAAAAAASSSSSSEEEEEEE, anybody can tellme what i'm doing wrong????
Thanks!
************************************

library ieee;
library std;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use ieee.std_logic_textio.all;

entity testbox is
end testbox;

architecture behaviour of testbox is
component general
port (
d: in STD_LOGIC;
syn: in STD_LOGIC;
clk: in STD_LOGIC;
z: out STD_LOGIC;
reset: in STD_LOGIC);
end component;

for all:general use entity WORK.general;

file outf: text open WRITE_MODE is "C:\veribest\workspace\outputs.txt";
file inf: text open READ_MODE is "C:\veribest\workspace\inputs.txt";

signal t_clk:std_logic;
signal t_syn:std_logic;
signal t_d:std_logic;
signal t_z:std_logic;
signal t_reset:std_logic;

begin
t_bbox : general
port map(t_clk, t_syn, t_d, t_z, t_reset);

process

variable i : integer;
variable in_l, out_l : line;
variable auxb: bit_vector(0 to 31);
variable auxs: std_logic_vector(0 to 4);
variable t : integer;

begin
i := 0;
auxb := (others=>'0');
auxs:= (others=>'0');

write(out_l, string'("Begin simulacion&quot);
writeline(outf,out_l);

while not endfile(inf) loop

-- Reset
t_reset<='1';
wait for 10ns;
t_reset<='0';
-- Fin Reset
t_syn<='1';

readline(inf, in_l);
read(in_l,auxb);

wait for 10ns;

for i in 0 to 4 loop
auxs(i):=TO_UX01(auxb(i));
end loop;

t:=CONV_INTEGER(unsigned(auxs));

for i in 0 to t loop
t_d<=TO_UX01(auxb(i));
t_clk<='1';
wait for 10ns;
t_syn<='0';
t_clk<='0';
wait for 10ns;
end loop;

wait for 10ns;
write(out_l,t_z);
writeline(outf,out_l);

end loop;

write(out_l, string'(&quot;End simulation&quot);
writeline(outf,out_l);
wait for 10ns;
end process;

end behaviour;

 

[chinna24]

hi!
in u r library files u included ieee and std but not work library so i guess thats why u r getting error. as general entity is in work library so we have to include work library while compiilation.
lets try by including the following code.

LIBRARY WORK;
USE WORK.general.ALL;
if u get any errors let me know and besure u include &quot;general&quot; code in u r nest posting;

thanks
PRAVEEN

 

[jas007]

hi Eljota
everything seems to be right with library files.the only problem is that u cannot directly input values to the signals.try declaring variables.......and then read thru them..after that assign these variables to the signals........

Thanks
Jas