Test Bench compilation error 1

[thushlak123]

When i compile the test bench code listed below i get the the following error.can someone help get rid of the error message.

Error: C:/VHDL/Lab5/testbench.vhd(15): Expected length is 1; string length is 4.
# ** Error: C:/VHDL/Lab5/testbench.vhd(16): Expected length is 1; string length is 4.
# ** Error: C:/VHDL/Lab5/testbench.vhd(17): Expected length is 1; string length is 4.
# ** Error: C:/VHDL/Lab5/testbench.vhd(18): Expected length is 1; string length is 4.
# ** Error: C:/VHDL/Lab5/testbench.vhd(20): VHDL Compiler exiting


-----CODE-----------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.Alutypes.ALL;

ENTITY TestBench IS

PORT (Data: OUT Operand;
OpCode: Out Operation);
END TestBench;

ARCHITECTURE simple OF TestBench IS
BEGIN
MainTest : PROCESS
BEGIN
Data <= "1111"; OpCode <= "101"; WAIT FOR 100 ns;
Data <= "0011"; OpCode <= "000"; WAIT FOR 100 ns;
Data <= "0001"; OpCode <= "001"; WAIT FOR 100 ns;
Data <= "1000"; Opcode <= "111"; WAIT;
END PROCESS MainTest;
END simple;

 

[avib]

The Data signal should be a four bit signal and the OpCode should be a 3 bit signal size but they are both defined as Operand.
The Operand type in your Alutypes library is probably defined as a 1 bit size.

Avi