Synthesizing VHDL function "*"

[mavian]

When i try to synthesize this code using Synopsys I get a class violation saying that input pins are not connected. This is caused by the res_mant_add <= t_mant1 * t_mant2; in my code. And its the input to some adder. Does anyone know how to fix it?

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

ENTITY hihi is
PORT (
F1 : in std_logic_vector(31 downto 0);
F2 : in std_logic_vector(31 downto 0);
clk : in std_logic;

norm_mant : out std_logic_vector(22 downto 0)
);
END hihi;

-- ***************************************************************************
ARCHITECTURE behavioral of hihi is
signal t_mant1, t_mant2 : std_logic_vector(23 downto 0);
signal res_mant_add, res_mant_final : std_logic_vector(47 downto 0);
signal res_mant : std_logic_vector(22 downto 0);

BEGIN

process begin
wait until rising_edge( clk );
t_mant1 <= '1' & F1(22 downto 0);
t_mant2 <= '1' & F2(22 downto 0);
end process;

process (t_mant1, t_mant2)
begin
-- multiply
res_mant_add <= t_mant1 * t_mant2;
end process;

process begin
wait until rising_edge( clk );
res_mant_final <= res_mant_add;
end process;

-- assign mantissa based on overflow (takes care of normalization)

with res_mant_final(47) select
norm_mant <=
res_mant_final(45 downto 23) when '0',
res_mant_final(46 downto 24) when others;
end behavioral

 

[RVSachin]

From your code, it appears that you are only using lower 24 bits of inputs F1 and F2. The other 8-bits of these inputs will be truncated because they are'nt required.

Also, the MSB of t_mant1 and t_mant2 are constants, tied to '1'; So, the flop associated with this bit will be removed.

All these issues can only lead to warning and I do n't believe that they can cause errors (...they shouldn't).