Synthesis of "wait until" with Xilinx Project Navigator

[annadorian]

Hi all!
I have a test bench for one of my designs and it works perfectly but currently I have to test my design with a real FPGA. So I have to synthesize it using Xilinx Project Navigator. Here I have some problems I can not synthesize fragment which is listed below and I do not know how to pass my problem. Because Xilinx does not support such kind of stuff Any ideas?

process
--some code which does not matter for my problem
while num_words < MAX_WORDS loop
wait until rising_edge(sys_clk_out);
--some code
end loop;
end process;

Thank you very much indeed in any advance.

 

[jeandelfrigo]

annadorian,

In my expirience wait until statements do not synthesize.

I am not sure what exactly you want to do but if you want to wait for the condition to become true and then to perform some actions I suggest you try it like this.

process(sys_clk_out)
begin
if rising_edge(sys_clk_out)
if (num_words > MAX_WORDS)
-- statements you want to perform
end if;
end if;
end process;

If you assign signals in this process then if the condition is not valid the signals will keep their value, so I would add an else to the inner if to make sure the signals have an alternate value for when the condtion is not true.

I hope I understood you intentions correctly. If not maybe you can provide me with some more information on what it is you are trying to do.

regards

jeandelfrigo