Synthesis of Program with multiple if statements in a process

[adithya1]

Hi Guys,

I've got a code that has lots of if statements and ifels statements. When i tried to synthesize the program, the signals on the ifels part were being identified as not connected. Please let me know how to deal with this problem.
I'm using Xilinx 6.1 ISE for the synthesis and implementation. Thanks in advance.

I have given a small section of the code. Other code blocks are similar in nature.

Signals like clk, reg_value... are the ones that are recognised as not connected. And the statements like rst <= '0', where starting and rst are signals are resulting in errors.

begin
*starting <= start;
*rst <= '0';
process (clk, rst, start, count_value1,count_value,outs)
begin
if(starting = '1') then
reg_value1 <= "0000000000";
count_value1 <= "0000";
starting <= '0';
rst <= '0';
elsif(rising_edge(clk)) then
*if(starting = '0') then
*if(count_value1 < "1010") then
*if (rst = '1') then
*reg_value <= "000000000";
*count_value <= "0000";
elsif (rising_edge(clk)) then
if (count_value < "1001") then
reg_value <= input & reg_value(8 downto 1);


Regards,
Adithya

 

[Magneto71]

Adithya,

you are hardcoding rst<= '0'; at the top of your code, hence the condition if(rst='1') is never true. Synthesis will find that everything until the corresponding end if; is never reached and gets optimised out. Also, do not need to have more than (starting, clk) in your sensitivity list