Synthesis of constants

[beemer]

Hello all,

I am trying to synthesize constant values. Previously, I had them as signals, where the logic produced actually fit my device (760 out of 784 total CLBs). As soon as I modified the signals to constants, the logic jumped to 1068 CLBs, and I could not fit onto the device anymore.

The reason for the modification is that synthesis does not accept initial values for signals and ties them to 0 instead, which is not what I am looking for.

Your help is much appreciated.

 

[vhdlverilog]

Synthesis tool doesnot support that.
instead u try this,use a reset signal in u'r entity.
and initialise it when reset comes
i hope u understood.
if (reset='1') then
thatsignal<=&quot;what ever value&quot;
else
do the remainig.

 

[beemer]

Hello,

Some synthesis tools do support constants. Basically it is setting it either to a VCC or a GND. I have resolved my issue because I used to be using the constants to convert from std_logic_vector to ints and vice versa, but I started using behavioural code which eliminated the need for that.


Thank you anyways.