synthesis and while = problem?

[myggel]

hi!

i wanted to sythesise a "while" loop.
but my synthesis tool (Xilink ISE Web Pack newest version) doesn't want to.
If the while loop is empty it's ok. but as soon as i put some decrement operator inside it doesn't synthesise.

Could anyone tell me why while isn't a good idea?

Thanks!

 

[BertVhdl]

Hi myggel,

Make sure that you use signals which are updated in the while loop in another place.

For example:

while Going loop
Count <= Count + 1;
wait until Clock = '1';
end loop;

A good synthesizer will throw this away, because Count isn't used anywhere.

Output <= Count;

while Going loop
Count <= Count + 1;
wait until Clock = '1';
end loop;

This while loop is synthesized, because Count is used with output "Output".

Hope this helps!