Hi,
I have FPGA with two clocks, one is 40Mhz and the other is 33Mhz.
Some of the logic signals are sampled by the 33Mhz clock and then connect to
another logic that uses the 40Mhz clock.
What is the best way of synchronizing these signal to the 40Mhz clock?
thanks,
Avi
I have FPGA with two clocks, one is 40Mhz and the other is 33Mhz.
Some of the logic signals are sampled by the 33Mhz clock and then connect to
another logic that uses the 40Mhz clock.
What is the best way of synchronizing these signal to the 40Mhz clock?
thanks,
Avi